Abstract: A semiconductor device includes a semiconductor substrate having a drift region of a first conductivity type; a base region of a second conductivity type in the semiconductor substrate; an emitter region of the first conductivity type in the semiconductor substrate; a first gate trench portion that is formed in the upper surface of the semiconductor substrate and is in contact with the emitter region and the base region; a second gate trench portion formed in the upper surface of the semiconductor substrate; a first electrical element electrically connected to the first gate trench portion; and a second electrical element electrically connected to the second gate trench portion, wherein a time constant of an RC circuit constituted by the second electrical element and the second gate trench portion is greater than a time constant of an RC circuit constituted by the first electrical element and the first gate trench portion.

Abstract: A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.

Abstract: A semiconductor device including a substrate having a dielectric layer over the substrate and a first conductive feature disposed within the dielectric layer. A metal nitride material is disposed directly on a top surface of the first conductive feature. A metal oxynitride material is disposed directly on a top surface of the dielectric layer, wherein the metal nitride and the metal oxynitride are coplanar. A second conductive feature is disposed over and interfacing the metal nitride material.

Abstract: In general, according to one embodiment, a semiconductor memory device includes: first and second variable resistance elements provided above a semiconductor layer; a first insulation layer provided on top surfaces and side surfaces of the first and the second variable resistance elements; and a first interconnect extending in a first direction and provided on the first insulation layer, at least a portion of the first interconnect being opposed to the side surfaces of the first and second variable resistance elements via the first insulation layer.

Abstract: A package includes a first dielectric layer, a device die over and attached to the first dielectric layer, an active through-via and a dummy through-via, and an encapsulating material encapsulating the device die, the active through-via, and the dummy through-via. The package further includes a second dielectric layer over and contacting the device die, the active through-via, and the dummy through-via. An active metal cap is over and contacting the second dielectric layer and electrically coupling to the active through-via. The active metal cap overlaps the active through-via. A dummy metal cap is over and contacting the second dielectric layer. The dummy metal cap overlaps the dummy through-via. The dummy metal cap is separated into a first portion and a second portion by a gap. A redistribution line passes through the gap between the first portion and the second portion of the dummy metal cap.

Abstract: A method for calibrating a cleaning device that has at least one sensor for detecting at least one state variable, including carrying out a calibration measurement, establishing an electronic connection between the calibration sensor and a controller of the cleaning device, and electronically transmitting the reference value to the controller; and comparing the reference value with at least one measurement value of the sensor of the cleaning device and adjusting at least one correction function in accordance with the comparison. At least one state variable is detected and at least one reference value is determined by means of at least one calibration sensor independently of the sensor of the cleaning device. Future measurement values of the sensor of the cleaning device are automatically corrected using the correction function.

Abstract: The present disclosure discloses a manufacturing method of a polycrystalline silicon thin film, which includes: forming a first amorphous silicon thin film; crystallizing the first amorphous silicon thin film to form a polycrystalline silicon thin film by applying an excimer laser annealing process; forming a second amorphous silicon thin film on a first surface of the polycrystalline silicon thin film; and etching until the second amorphous silicon thin film is completely removed toward a direction of the polycrystalline silicon thin film from the second amorphous silicon thin film by applying a dry etching process. The present disclosure further discloses a manufacturing method of a thin film transistor array substrate which includes the steps of manufacturing an active layer: forming a layer of a polycrystalline silicon thin film according to the previous polycrystalline silicon thin film; and etching the polycrystalline silicon thin film to form a patterned active layer.

Abstract: A method for forming a film that covers a side wall of a through hole in a substrate having the through hole, the method including, in the following order, the steps of providing a substrate having a through hole that passes therethrough from a first surface to a second surface, which is a surface opposite to the first surface, forming, on the first surface, a lid member that blocks an opening of the through hole open on the first surface, recessing, in a direction away from the first surface, a surface of the lid member that blocks the opening by removing part of the lid member through the opening, and forming a film that covers the side wall of the through hole.

Abstract: The present disclosure relates to a solid-state imaging device and an electronic device that are configured to suppress the occurrence of noise and white blemishes in an amplification transistor having an element separation region which is formed by ion implantation. An amplification transistor has an element separation region formed by ion implantation. A channel region insulating film which is at least a part of a gate insulating film above a channel region of the amplification transistor is thin compared to a gate insulating film of a selection transistor, and an element separation region insulating film which is at least a part of a gate insulating film above the element separation region of the amplification transistor is thick compared to the channel region insulating film. The present disclosure can be applied to, for example, a CMOS image sensor, etc.

Abstract: The embodiments of the present disclosure relate to a power package module of multiple power chips and a method of manufacturing a power chip unit. The power package module of multiple power chips includes: a power chip unit including at least two power chips placed in parallel and a bonding part bonding the two power chips; a substrate supporting the power chip unit and including a metal layer electronically connecting with the power chip unit; and a sealing layer isolating the power chip unit on the substrate from surroundings to seal the power chip unit; the bonding part and the sealing layer are made from different insulated material, the distance of a gap between the two power chips placed in parallel is smaller than or equal to a preset width, and the bonding part is filled in the gap, insulatedly bonding the two power chips placed in parallel.

Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor is a grading strained stressor including multiple graded portions formed at graded depths. The first stressor is configured to create one of a graded compressive stress or a graded tensile stress.

Abstract: One illustrative method disclosed herein includes, among other things, forming a vertically oriented channel semiconductor structure above a substrate, performing an epi deposition process to simultaneously form at least a portion of a bottom source/drain region and at least a portion of a top source/drain region during the epi deposition process and, after performing the epi deposition process, forming a gate structure around a portion of the vertically oriented channel semiconductor structure.

Abstract: A method includes forming a film on a substrate by performing a cycle n times (where n is an integer equal to or greater than 1), the cycle including alternately performing: performing a set m times (where m is an integer equal to or greater than 1), the set including supplying a precursor to the substrate and supplying a borazine compound to the substrate; and supplying an oxidizing agent to the substrate.

Abstract: A stack type sensor package structure includes a substrate, a semiconductor chip disposed on the substrate, a frame disposed on the substrate and aside the semiconductor chip, a sensor chip disposed on the frame, a plurality of wires electrically connecting the sensor chip and the substrate, a transparent layer being of its position corresponding to the sensor chip, a support maintaining the relative position between the sensor chip and the transparent layer, and a package compound disposed on the substrate and partially covering the frame, the support, and the transparent layer. Thus, through disposing a frame within the stack type sensor package structure, the structural strength of the overall sensor package structure is reinforced, and the stability of the wiring of the sensor chip is effectively increased.

Abstract: A system and method for qualitative analysis of time progressive signals, comprising: a qualitative signal analysis module, comprising at least a processor, a memory, and a long term storage device; and an output processor module comprising at least a processor a memory and a network interface has been devised. The qualitative signal analysis module retrieves signal data over time and applies pre-programmed protocols to compare multiple aspects of the signal data to derive meaningful data. The output processor module encodes data generated by the qualitative signal analysis module for use in subsequent analytical steps such as further manipulation, classification or long term storage.

Abstract: A computer-implemented system and method to evaluate building heating fuel consumption is described. The evaluation can be used for quantifying personalized electric and fuel bill savings. Such savings may be associated with investment decisions relating to building envelope improvements; HVAC equipment improvements; delivery system efficiency improvements; and fuel switching. The results can also be used for assessing the cost/benefit of behavioral changes, such as changing thermostat temperature settings. Similarly, the results can be used for optimizing an HVAC control system algorithm based on current and forecasted outdoor temperature and on current and forecasted solar irradiance to satisfy consumer preferences in a least cost manner. Finally, the results can be used to correctly size a photovoltaic (PV) system to satisfy needs prior to investments by anticipating existing energy usage and the associated change in usage based on planned investments.

Abstract: Provided is a semiconductor device including a substrate having a P-type conductivity, a buried layer having an N-type conductivity, an NPN bipolar junction transistor (BJT), and a first well region having the P-type conductivity. The buried layer is located on the substrate. The NPN BJT is located on the buried layer. The first well region is located between the buried layer and the NPN BJT. The NPN BJT is separated from the buried layer by the first well region.

Abstract: A method of manufacturing a light emitting device package is provided. The method includes preparing a film strip including one or more light blocking regions and one or more wavelength conversion regions, preparing light emitting devices, each including one or more light emitting regions, bonding the film strip to the light emitting devices so as to dispose the one or more wavelength conversion regions on the one or more light emitting regions of each of the light emitting devices, and cutting the film strip and the light emitting devices into individual device units.

Abstract: Embodiments of the disclosure provide a bearing substrate and a fabrication method for a flexible display device, which relate to the field of display technology and may achieve a uniform separation between a flexible substrate and bearing substrate, and not cause damage to the flexible substrate and the display element. The bearing substrate comprises a first sub-bearing substrate and a second sub-bearing substrate. The first sub-bearing substrate has a plurality of through holes, and the second sub-bearing substrate has a plurality of protrusions that are in one-to-one correspondence with the protrusions. The protrusions and the through holes are configured such that the protrusions are capable of passing through the through holes when assembling the first sub-bearing substrate with the second sub-bearing substrate, so that the protrusions are flush with a surface of the first sub-bearing substrate and spliced together with the surface.

Abstract: Examples of techniques for determining robustness of a discrete fracture network (DFN) permeability estimate are disclosed. In one example implementation according to aspects of the present disclosure, a method may include: receiving a DFN of an earth formation of interest, the DFN comprising a plurality of connected fractures; determining a directional equivalent permeability of the plurality of connected fractures of the DFN using a numerical upscaling method; and determining the robustness of the directional equivalent permeability.