Patents Examined by Charles D. Miller
  • Patent number: 4804941
    Abstract: An improved circuit for compensating an input/output characteristic linearity of a parallel comparison type analog-to-digital converter which reduces a wasteful consumption of current in the linearity compensation circuit. In the improved linearity compensation circuit, a dummy circuit having the same construction as a bias circuit of each comparator of the A/D converter is installed for providing a current I.sub.E which is an amplification of an input current by means of the input circuit of each comparator, a first current multiplier is installed for providing a multiplied current kI.sub.E on the basis of the current provided by the dummy circuit, an amplifier is installed for providing a current ki which corresponds to a multiplication of the current i by an amplification factor of the input circuit, and a second current multiplifier is installed for providing another multiplied current kli which is a multiplication of the current ki by l.
    Type: Grant
    Filed: February 8, 1988
    Date of Patent: February 14, 1989
    Assignee: Sony Corporation
    Inventor: Yoji Yoshii
  • Patent number: 4801923
    Abstract: A method and apparatus are disclosed for converting a digital TACAN output into an analog potentiometer input suitable for an analog navigation computer. The apparatus includes an input register for temporarily storing a digital TACAN output signal. A nines complement generation circuit is utilized to generate the nines complement of the digital TACAN output signal and the nines complement is temporarily stored in a second register. The data in each register is then utilized to control one of two identical resistive circuits which are coupled to a common output node so that the total resistance in both circuits is always equal to a selected total resistance. In a preferred embodiment of the present invention, a plurality of optically coupled solid state relays are utilized to control the resistive circuits.
    Type: Grant
    Filed: July 20, 1984
    Date of Patent: January 31, 1989
    Assignee: LTV Aerospace & Defense Company
    Inventors: Robert J. Schwartz, Frederick G. Reinagel
  • Patent number: 4796006
    Abstract: An analog output system coupled to a digital system bus (1, FIG. 1) comprises a RAM (8) in which digital data may be input from the system bus. The data is converted into analog form by digital-to-analog converters (30-37) in either continuous mode or intermittent mode, depending upon the contents of control/status register (18). The system also comprises interrupt logic (6), bus arbitration control logic (16), and reconstruction filters (40-47). A watchdog timer (50) zeroes all outputs which have not been accessed via the system bus (1) within a specified time period. The conversion rate can be controlled either by an internal timer (52) or by an external trigger (57). The output channel configuration and conversion frequency are fully software programmable.
    Type: Grant
    Filed: November 20, 1986
    Date of Patent: January 3, 1989
    Assignee: Burr-Brown Limited
    Inventors: Kenneth W. Murray, Joseph Purvis
  • Patent number: 4792788
    Abstract: A rotatable member having multiple discrete positions between opposite ends of a normal path of movement is provided with two (or three) parallel, encoded tracks having different patterns of distinct, serial sections. These tracks cooperate with relatively stationary probes of a position sensor. As the rotatable member moves from position to position, the sensor will produce a family of two (or three) separate binary signals that changes states as the probes detect boundaries between successive sections of the tracks with which they respectively communicate, and the patterns of the encoded sections are so selected that the sequence of state changes when the rotatable member is approaching a predetermined mid position will differ from the sequence when the member is moving away therefrom.
    Type: Grant
    Filed: November 23, 1987
    Date of Patent: December 20, 1988
    Assignee: General Electric Company
    Inventor: Ajith K. Kumar
  • Patent number: 4792786
    Abstract: Integrated circuits in the form of a multiplexer, an instrumentation amplifier, a sample-and-hold amplifier, and an A/D converter are mounted on a single substrate, forming a data acquisition system capable of selecting one of a number of analog signals and converting it into a digital number. The resulting package is mounted in a leadless chip carrier (LCC) suitable for surface mounting.
    Type: Grant
    Filed: March 2, 1988
    Date of Patent: December 20, 1988
    Assignee: Burr-Brown Limited
    Inventors: Charles H. Lewis, James P. Edgar, Heinz-Juergen Metzger
  • Patent number: 4791407
    Abstract: A communication system and method for transmitting information in the form of binary digital data to be transmitted is encoded into two separate two level sequences S1 and S2 such that the first occurrence of a logic "1" is encoded into the same level in both sequences and each subsequent occurrence of a logic "1" is encoded into the level opposite of the previous level representing a logic "1" in each of the sequences S1 and S2, and the first occurrence of a logic "0" is encoded into opposite levels in sequences S1 and S2 and every subsequent occurrence of a logic "0" is encoded into the level opposite of the previous level representing a logic "0" in each of the sequences S1 and S2. The two encoded streams drive optical signal producing means of respectively different wavelengths and the two optical signals are transmitted over a wavelength-multiplexed fiber-optic link.
    Type: Grant
    Filed: August 4, 1987
    Date of Patent: December 13, 1988
    Assignee: Trustees of Columbia University in the City of New York
    Inventors: Paul R. Prucnal, Philippe A. Perrier
  • Patent number: 4782325
    Abstract: For reducing the redundancy ratio of an entity key set, from very high ratios when encoded into conventional I/O code-words, down to a ratio close to zero, a non-redundant number code representation is employed in an encoder/decoder in lieu of a conventional multiple code-word representation, each member of the number code representing a member of the entity key set. Such a number code encoder/decoder may hold in store and provide access to an entity key set representing a set of 65535 different textual or lexical words, thereby using a 16 bit fixed length number code. Code-words representing such code numbers would require 16 bits of storage each if being held in store, however, such code numbers are produced using two alternative methods, (i) as relative address values of individual storage locations within a string of storage locations, e.g., a string of 8 bit byte locations, or (ii) as marked bit counts within a bit map representing the stored set.
    Type: Grant
    Filed: September 9, 1986
    Date of Patent: November 1, 1988
    Inventors: Hakan Jeppsson, Tina Jeppsson, Martin V. I. Jeppsson
  • Patent number: 4782326
    Abstract: A data interface circuit for use when interfacing between two communication links communicating frames of digital data in PCM and ADPCM formats is provided. The data interface circuit provides control information for selecting one of a plurality of algorithms to control the transformation of data between a plurality of PCM and ADPCM formats. A single encoded control signal is utilized to establish frame boundaries and to select a predetermined one of the plurality of algorithms to use in converting between PCM and ADPCM data.
    Type: Grant
    Filed: October 1, 1987
    Date of Patent: November 1, 1988
    Assignee: Motorola, Inc.
    Inventor: David E. Bush
  • Patent number: 4782323
    Abstract: A switched capacitor circuit for use in a digital-to-analog converter, an analog-to-digital converter, or other digitally controlled circuit is disclosed. The switched capacitor circuit includes first and second arrays (30, 40) of switched capacitors of substantially identical value, each capacitor having a switched terminal. The switched capacitor circuit further includes a decoding circuit (20) responsive to a digital input having a decimal value N for providing control signals for each of the capacitor arrays. Logic circuitry (33, 43, GC(I)) responsive to the control signals is included for sequentially switching the switched terminals of L and M capacitors respectively of the first and second switched capacitor arrays in a predetermined sequence so as to maintain the geometrical centroid of the switched capacitors at a substantially constant location, where the sum of L and M is equal to N.
    Type: Grant
    Filed: April 4, 1988
    Date of Patent: November 1, 1988
    Assignee: Hughes Aircraft Company
    Inventor: Charles H. Lucas
  • Patent number: 4779074
    Abstract: A convertor for converting an analog signal to a digital pulse comprises a switching capacitor which is charged by a differential analog signal supplied to the switching capacitor over an input circuit. The capacitor is discharged over an output circuit with the aid of a constant current supply. The charge level of the capacitor is proportional to the analog signal so that the time it takes the capacitor to discharge to a selected low charge level, is proportional to the analog signal. This time period is used by a microprocessor control to generate a digital pulse having a pulse equal to the discharge time for the capacitor. The microprocessor also selectively connects the input and output circuits to the capacitor for respectively charging and discharging the capacitor.
    Type: Grant
    Filed: September 14, 1987
    Date of Patent: October 18, 1988
    Assignee: The Babcock & Wilcox Company
    Inventors: Rowland E. Whitford, Edward Bastijanic
  • Patent number: 4777470
    Abstract: In a successive approximation analogs-to-digital converter, a successive approximation register (SAR) includes an N bit, edge triggered shift register, each bit including a master-slave flip-flop. The output of each shift register bit is applied to a latch input of a D-type latch and to one input of a two-input gate that performs a logical ANDing function. Another input of the gate is connected to an output of the latch. The D input of each of the N latches is connected to an output of a corresponding comparator, which compares an analog input signal to a signal produced by an N bit digital-to-analog converter (DAC) in response to successive approximation numbers produced by the SAR. The gate outputs are connected to digital inputs of the DAC. A "0" propagates through the shift register at the DAC conversion rate.
    Type: Grant
    Filed: September 28, 1987
    Date of Patent: October 11, 1988
    Assignee: Burr-Brown Corporation
    Inventors: Jimmy R. Naylor, Joel M. Halbert, Wallace Burney
  • Patent number: 4775852
    Abstract: A high precision analog to digital converter comprises the combination of an imperfect or low resolution digital to analog converter having an error function known in terms of orthonormal components and an error compensating device capable of generating correction terms which do not interact with one another. The correction terms are based on orthonormal components namely, the Walsh function components, of each signal level to be compensated. At most only one weighting value per bit is required, the combination of which will compensate for errors of any bit combination. In a specific embodiment employing feedback compensation, the output of the low resolution converter and of the compensating device may be summed to produce a high performance, high precision converter with increased accuracy and resolution.
    Type: Grant
    Filed: July 13, 1987
    Date of Patent: October 4, 1988
    Assignee: Schlumberger Systems & Services, Inc.
    Inventor: Edwin A. Sloane
  • Patent number: 4774498
    Abstract: An analog-to-digital converter (10) comprises a set of comparators (12a-12f) for providing a set of different output signals whose logic states are a function of an analog input signal voltage and one or more reference voltage signals supplied by a resistive network (16). The comparators are connected to a decoder (20) for processing the thermometer code outputs of the comparators to generate a digital word output corresponding to the voltage amplitude of the analog signal. Several of the comparators are also connected to an error checking network (22), including a preconditioning circuit (100) and a detection circuit (102) for processing these comparator outputs to provide an error signal whenever one or more of the comparators are not operating properly. The error checking network and decoder are connected to an error correction circuit (26) for correcting the digital word signal in accordance with the error signal.
    Type: Grant
    Filed: March 9, 1987
    Date of Patent: September 27, 1988
    Assignee: Tektronix, Inc.
    Inventor: Einar O. Traa
  • Patent number: 4774500
    Abstract: A data compaction method, for writing data in highly compact binary form in a data storage medium using a microprocessor, compresses serially occurring transaction values in a limited memory space by substituting prefix codes for previously occurring values and for commonly occurring previous values. The previous values are listed and updated on tables by the microprocessor so that they are indexed to the prefix codes adaptively to changing local values and changing common values over time. The data compaction method is particularly suitable for an account card having a limited, non-erasable memory used in an automated transaction terminal for maintaining an account record of transactions in frequently recurring amounts. A postage metering terminal is operated by the account card, in which an initial balance has been written and each purchase of postage is recorded. A current balance is recomputed by parsing the previously recorded data.
    Type: Grant
    Filed: October 21, 1987
    Date of Patent: September 27, 1988
    Assignee: Wright Technologies
    Inventor: Ronald D. Lichty
  • Patent number: 4771266
    Abstract: An A/D converter including a D/A converter which generates a reference voltage; a comparator which compares a sampled analog input voltage with the reference voltage; and a sequential comparator control circuit which repeats the comparison steps that input a digital value into the D/A converter in accordance with the result of the determination by the comparator to obtain the result of the conversion. The sequential comparator control circuit inputs an initial digital value to the D/A converter so that a reference voltage larger than one half (1/2) of a maximum allowable value of the analog input is supplied to the comparator at the time the A/D conversion commences. The sequential comparator control circuit holds or changes the content of the digital value input to the D/A converter at each comparison step in accordance with the result of the comparison. The comparison step is commenced with any bit except the most significant bit.
    Type: Grant
    Filed: October 8, 1986
    Date of Patent: September 13, 1988
    Assignee: Fujitsu Limited
    Inventor: Hideo Nunokawa
  • Patent number: 4769630
    Abstract: An incremental optical code reader of the wholly integrated type including a reading assembly, a pair of photodiodes, a differential amplifier receiving the outputs of the photodiodes and a trigger connected to the output of the amplifier. An electronic assembly with "exclusive OR" logic gates, AND logic gates and OR logic gates, receiving the outputs of the triggers for the channels and feeding into the outputs.
    Type: Grant
    Filed: July 23, 1986
    Date of Patent: September 6, 1988
    Assignee: M.C.B.
    Inventors: Jacques Taillebois, Paul Gambs, Jean-Marie Renaud
  • Patent number: 4768015
    Abstract: An A/D converter comprises a first reference voltage source generating a first group of reference voltages distributed in a first voltage range, and a first A/D converting circuit connected to receive an analog signal and the first group of reference voltages for generating a first digital signal. The A/D converter also includes a second reference voltage source having a bias input receiving a bias voltage and generating a second group of reference voltages which are distributed in a second voltage range smaller than the first voltage range and which are biased by a bias voltage inputted to the bias input, and a second A/D converting circuit connected to receive the analog signal mentioned above and the second group of reference voltages for generating a second digital signal. A calculator is provided to receive the first and second digital signals for generating a third digital signal having a resolution higher than that of the first digital signal.
    Type: Grant
    Filed: September 8, 1987
    Date of Patent: August 30, 1988
    Assignee: NEC Corporation
    Inventor: Tatsuyuki Amano
  • Patent number: 4766417
    Abstract: An automatic offset compensating bipolar A/D converter circuit includes an A/D converter and a feedback circuit, which automatically compensates offset error between a specific level of input having analog voltage and a specific output code of output digital value corresponding to that input analog voltage. The A/D converter can convert the input analog voltage, which includes residual noises more than 1 LSB, into an output digital value. The feedback circuit can add a compensation voltage to the input analog voltage so as to equalize the posibilities of occurrence of codes which are more than and less than a specific output code of an output digital value to each other in accordance with an output digital value.
    Type: Grant
    Filed: June 1, 1987
    Date of Patent: August 23, 1988
    Assignee: Sony Corporation
    Inventors: Jun Takayama, Takeshi Ninomiya
  • Patent number: 4764750
    Abstract: An analog-to-digital converter includes a plurality of digital-to-analog converting circuits, a control circuit connected to the digital-to-analog converting circuits to control the condition of the respective digital-to-analog converting circuits, a comparator having a first input connected commonly to outputs of the digital-to-analog converting circuits and a second input connected to receive a reference voltage, and a successive approximation register connected to an output of the comparator and adapted to control the control circuit. The control circuit is adapted to generate control signals to the respective digital-to-analog converting circuits in one-to-one relation so that the output potentials of the digital-to-analog converting circuits are successively incremented one after one by a potential corresponding to one bit.
    Type: Grant
    Filed: June 19, 1987
    Date of Patent: August 16, 1988
    Assignee: NEC Corporation
    Inventor: Shigeru Kawada
  • Patent number: 4763107
    Abstract: A 12 bit, 10 megahertz subranging analog-to-digital converter produces a sampled analog input signal. The sampled analog signal is converted by an MSB flash encoder to a 7 bit MSB word that is converted to an analog signal by a 7 bit DAC having 14 bit accuracy. The result is subtracted from the sample analog signal to produce a residue signal by means of a high speed amplifier having first and second multiplexed differential input stages, the first input stage having differential inputs receiving the sampled analog input signal and the analog signal produced by the 7 bit DAC. The second differential input stage has one input connected to ground and the other input resistively coupled to the output of the high speed amplifier. The output of the high speed amplifier is resistively coupled to the second input of the first and second differential stages. The multiplexed input high speed amplifier produces an intermediate input level until the output of the DAC is stable.
    Type: Grant
    Filed: August 7, 1987
    Date of Patent: August 9, 1988
    Assignee: Burr-Brown Corporation
    Inventors: Myron J. Koen, Thomas R. Anderson, Joel M. Halbert