Abstract: For the distortionless conversion of an audio or like data signal from analog to digital form as by pulse code modulation, the input data signal is time division multiplexed with an analog dither (white noise) signal to provide a multiplex signal composed of the analog dither signal and an analog data/dither signal, the latter being an addition of the analog data and dither signals. Then the multiplex signal is converted from analog to digital form by one and the same analog to digital converter. The subsequent removal of the digital dither component from the digital data/dither signal provides a digital data signal as a replica of the input analog data signal. The use of the same converter for the conversion of both dither signal and data/dither signal from analog to digital form makes possible the maximum possible removal of the dither from the digital data/dither signal.

Abstract: Apparatus and a method for use therein are disclosed for an analog signal processor, particularly one suited for use in nuclear power plant applications, which converts analog process signals to digital form and employs continuous on-line automatic calibration in order to accurately compensate for gain and bias errors occurring in its input analog circuitry.

Abstract: A guided-wave electrooptic analog-to-digital converter utilizes a multiple wavelength optical source as a sampling source to minimize the number of interferometers needed for conversion of an analog signal with a given resolution. A reduction in the number of interferometers reduces the capacitive impedance of the analog signal input and facilitates driving the converter with conventional R.F. amplifiers. The multiple-wavelength signal consists of a combination of a plurality of signals with wavelengths which are substantially binary multiples of the shortest wavelength. The signals are passed together through a conventional Mach-Zehnder interferometric modulator and the interferometer output is split back into a plurality of output beams each with a single wavelength. Each of the output beams represents a bit of the digitized signal. By increasing the number of different wavelengths in the sampling signal, higher resolutions in the output signal can be obtained with a single interferometric modulator.

Abstract: A time-discrete amplitude-continuous or a time-discrete amplitude-discrete signal is converted in to a 1-bit encoded signal by means of a quantizer, the quantization-error signal being fed back via a loop filter. The transfer function of the loop filter is given by H(Z)=1-(Z-b).sup.n /(Z-a).sup.n, where n.gtoreq.3, b.perspectiveto.1 and 0<a<b. In order to preclude, the input signal of the loop filter is limited by a limiter.

Abstract: In a comparator circuit, first and second latchable circuits are connected in cascade between the output of an amplifying stage and the input of a decoder to enable the comparator to operate at significantly higher frequencies with lower error levels. An input signal, to be sampled, and a reference signal are applied to the input of the amplifying stage and a "sampled" signal indicative of the difference between the input and the reference is produced at the output of the amplifying stage. The "sampled" signal produced at the output of the amplifying stage is first processed, via the first latchable circuit operated in a regenerative mode to enhance the signal, during one time interval. The enhanced signal is then processed via the second latchable circuit operated in a regenerative mode tending to further enhance the signal, during a second, succeeding, time interval, for application to the decoder.

Abstract: Methods are set forth for constructing encoding and decoding state machines for preselected variable length fixed rate (2,7) codes. These state machines convert a variable length code to a state dependent fixed length fixed rate (2,7) code. Methods and apparatus are also disclosed for implementing a state dependent fixed length fixed rate (2,7) coding scheme in a manner that is simpler and inherently more reliable than the implementation of the corresponding variable length fixed rate (2,7) code. In addition, the disclosed methods and apparatus for implementing the state dependent code preserve the error recovery features of a variable length fixed rate (2,7) coding scheme.

Abstract: In a data encoding/decoding circuit, a data encoding circuit includes a first clock, a first time setting circuit, a first random number generator, and a converter for receiving transmission data and converting the transmission data into output data with frame sync signals. A data decoding circuit includes a second clock, a second time setting circuit, a frame sync extracting circuit, a time correction circuit for correcting the time of the second clock, a second random number generator, and an inverter for inverting output data from the frame sync extracting circuit with a random number from the second random number generator and outputting the inverted data as decoded data.

Abstract: An optical detector circuit for a photometric instrument for providing a high precision, low cost A/D conversion of a detected optical signal. A sampled signal is integrated in a sample signal integrator while a reference signal integrator is integrated in a reference signal integrator. Using dual slope techniques, the integrated reference signal is provided as an input signal to the sample signal integrator during a de-integration cycle to provide a ratio of the detected signal to the reference signal, useful in nephelometers. An inverted blanking signal may also be integrated in the sample integrator prior to an integration of the sample signal to improve the accuracy of the dual slope integration. The period of integration is selected as a multiple of the primary sources of interfering noise such as power line and flourescent light frequencies.

Abstract: An integrated semiconductor circuit which contains both a microprocessor as well as an analog-to-digital converter. Two D/A converters are allocated to an A/D converter. One of the D/A converters generates a internal base potential from an externally supplied fixed base potential and an externally supplied fixed reference potential under the direction of the microprocessor. The other one generates a internal reference potential from the two external potentials. The two internal potentials form the reference voltage which serves for the A/D conversion according to the principle of successive approximation. By so doing, the same circuit can be controlled by measuring points having different voltage ranges without the converter having to be provided with additional comparison stages. These are involved in comparison to the A/D conversion to be applied and serve the purpose of increasing the resolution.

Abstract: In an analog-to-digital converter circuit comprising a comparison circuit per tap of a potential divider. The comparison circuits are arranged in groups each controlling a respective differential amplifier. In a group only one output of each comparison circuit is connected to an output of the subsequent comparison circuit operating in the opposite sense and the odd outputs of the group of outputs thus obtained are connected via a first group of emitter followers to a first input of one of the differential amplifiers, while the even outputs are connected via a second group of emitter followers to a second input of this differential amplifier.

Abstract: In an integrated circuit for transcoder, a subtractor generates a signal representing a difference between an input speech signal and a prediction signal. This signal is transferred to a quantizing unit. The unit quantizes an output signal from the subtractor, and generates a predictive encoded signal. An inverse quantizing unit generates a difference signal. A predictor filter generates the prediction signal to be supplied to the subtractor. A signal path changing unit made up of electronic switches responds to a mode select signal to suitably change an electric connection among the subtractor, the quantizing unit and the reverse quantizing unit, whereby the integrataed circuit device can function as an ADPCM encoder or an ADPCM decoder.

Abstract: A 12 bit, 10 megahertz subranging analog-to-digital converter feeds a sampled analog input signal forward, without delay or attenuation, to a summing node. The sampled analog signal is converted by an MSB flash encoder to a 7 bit MSB word that is converted to an analog signal by a 7 bit DAC having 14 bit accuracy. The result is subtracted from the sampled analog signal to produce a residue signal. A MOSFET isolation switch coupled between the summing node and the input of a high speed amplifier isolates the amplifier until the residue signal is stable, to prevent overdriving of the amplifier. A positive error voltage is added to the reference voltage inputs of the MSB flash encoder to enable use of a digital error correcting circuit that does not need to operate on negative binary numbers.

Abstract: An apparatus for producing, from four consecutive unconstrained data bits in a bit string, a run-length-limited (RLL) encoded symbol consisting of three coded data bits. The internal state of the encoder is described by one state bit. The encoder performs RLL (1,7) encoding on a bit-by-bit basis, and can be cascaded in parallel to perform encoding on sequential, equally-sized groups of unencoded data bits. An attractive feature of the encoder is that it can be cascaded to simultaneously encode consecutive bytes of data.

Abstract: On encoding a cluster and run sequence comprising clusters of non-zero signal elements and runs of zero signal elements into a code sequence with application of a compression encoding scheme selectively to the clusters and without application of the encoding scheme to the runs, a mode code is used to indicate application of the encoding scheme to each selected cluster and to represent a zero signal element next preceding the selected cluster in a next preceding run. In the code sequence, the mode code next precedes a succession of amplitude codes representative of the selected cluster and next succeeds a run length code preferably representative of that run length of the next preceding run from which the next preceding zero signal element is reduced. Alternatively, the mode code may indicate switching between application and non-application of the encoding scheme to partial sequences each of which starts with a cluster next succeeded by a run.

Abstract: A digitally programmable infinite impulse response (IIR) filter particularly useful as a temporal averager. The filter comprises a voltage mode multiplying digital/analog converter (12) and two sample-and-hold circuits (10, 16). The first sample-and-hold circuit receives the input signal to the system and supplies its output signal to the reference voltage input terminal of the DAC. The second sample and hold circuit has its input terminal connected to the voltage output terminal of the DAC and has its output connected to the analog ground terminal of the DAC. A digital input code (D) supplied to the DAC controls its gain and the degree of noise rejection provided by the filter, by altering the frequency response of the filter.

Abstract: An A-D converter which oversamples the input analog signal, at a frequency greater than the Nyquist frequency, and achieves high precision linear coding by performing simple operations at a high sampling frequency f.sub.H while complicated operations are performed at a low sampling frequency f.sub.s. The high sampling frequency may be reduced to the low sampling frequency through a two-step reduction using a sampling frequency converter to reduce the frequency to an intermediate frequency f.sub.M and an integrator/sampler to reduce the sampling frequency further to f.sub.s or directly with the use of an FIR filter having a frequency characteristic in which attenuation is large in the out-of-band and gain deviation is small in-band.

Abstract: A digital-to-analog converter capable of bi-directional output currents which is especially useful for direct conversion of digitally encoded audio signals. The converter is made up of a plurality of bit-cell circuits, one per bit in the digital number to be decoded, each fed by a pair of current sources of identical magnitude and opposite direction. Each bit-cell is a bridge circuit of four controllable devices, controlled by a data bit and its complement so that the current flow through the current output of the cell reverses based upon the value of the data bit. The outputs of the bit-cells are paralleled, and the current source pairs are scaled in a binary fashion, so that each bit-cell steers a current which is one-half that of the next-higher cell.In a preferred embodiment, the current sources are made up of two binary scaled current generators using R-2R resistor networks to scale currents from two reference sources. The two references are preferably linked to each other through a feedback circuit.

Abstract: Resolvers are in common use as angular position sensing devices. Such resolvers normally require difficult to generate sine-wave excitation signals, and extensive decoding circuitry for producing an output signal related to angular position. The subject apparatus utilizes a generator to produce a rectangular-wave timing signal. A logic circuit receives the timing signal and responsively produces first and second rectangular-wave excitation signals, which are delivered to respective stator coils of a resolver. A decoding circuit receives one of the excitation signals and the phase encoded signal magnetically induced in the rotor coil of the resolver, and produces an angular position signal having a duty cycle responsive to the phase difference between the received signals.

Abstract: Digital companding without range bits involves comparison of a digital input with predetermined boundaries separating a plurality of numerical ranges, detection of a numerical range to which the digital input belongs, generation of an off-set unique to each numerical range, bit-shifting of the digital input, and addition of the bit-shifted input with the generated off-set to provide a companded digital output which is in one-to-one correspondence to the digital input. The off-set values are stored in a memory.

Abstract: A system and apparatus for compressing redundant and non-redundant binary data generated as part of an operation of a time and attendance terminal in which the data represents the time an employee is present during working hours. The first data entry includes the date and the time the employee operates the terminal together with other data identifying the employee which is stored in a circular buffer. The time of day data includes the hour and the minutes of the keyboard operation. Subsequent data entries include redundant data such as the date and the hour of the terminal operation which may not change and non-redundant data such as the minutes that pertain to the terminal operation together with data identifying the operator. After the redundant and non-redundant data of the first data entry are stored, only the non-redundant data of each subsequent data entry is stored.