Abstract: An analog-to-digital or digital-to-analog converter comprises: a signal input terminal an integrator connected to the signal input terminal; a plurality of constant current sources connected to the integrator so that the integrator is supplied with respective constant currents; a first counter having a first predetermined number of bits for higher significant bits and a second counter having a second predetermined number of bits for lower significant bits; and a clock signal generator for generating a first clock signal having a first clock frequency and being supplied to the first counter and a second clock signal having a second frequency higher than the first clock frequency and being supplied to the second counter; and currents of the plurality of constant current sources are respectively determined according to the first and second predetermined numbers of bits and the first and second clock frequencies of the first and second clock signals, respectively.

Abstract: A system and apparatus for encoding a set of input vector components by initiating a sequential search through a codebook memory to put out a series of associated error code vectors which can be compared in sequence over a period of time in order to select the minimum error code vector (best fit). A clocking-sequencing means enables an output latch to hold (after termination of the sequence period) the index number which represents the particular error code vector presently having the minimum distortion. Each new set of input vector components will be sequenced to search for the minimum error code vector (and index) for that particular set of input vector components.

Abstract: A steady or slowing changing analog signal affected with noise is sampled and held at the sampling rate of a following analog to digital converter and has a rectangular a.c. signal superimposed on it before it is supplied to the converter. This is done in such a way that when the analog signal is in the middle range between quantization steps, the least significant bit (LSB) is well defined. When the analog signal is close to a quantization threshold, the superimposed rectangular pulses change the LSB values back and forth and comparison of successive values is used to suppress changes in LSB value. On the other hand, if the analog signal is changing more rapidly through quantization steps, the circuit does not interfere with digital output changes. The system can be used during the vertical blanking intervals of a television signal for digitizing an analog voltage corresponding to a blending voltage for a video signal.

Abstract: A redundant decoder for use in a predecoded memory scheme includes a plurality of predecoding circuits each having an output and each having inputs coupled to selected address signals. The outputs of the predecoding circuits are applied to the inputs of a smaller group of decoding circuit. In addition, the outputs of the predecoding circuits are coupled to the gate electrodes of one of a plurality of series coupled field effect transistors each having a laser blowable fuse coupled across its source drain path. Should one of the decoding circuits prove to be operating improperly, is only necessary to blow the fuses across the individual field effect transistors whose gate electrodes are coupled to the predecoding circuit outputs which served as inputs to the bad gate. In this manner, the output of the stack will go high only when the output of the bad decoding circuit should go high.

Abstract: A measured voltage is converted into a digital value according to the follow-up principle. A compensation signal is added to the measuring signal so that the mean value of both signals becomes zero. The compensation signal is formed from at least two auxiliary compensation values which are each a square wave signal having a fixed frequency and a keying ratio which is adjustable independently of the other square wave voltage. The keying ratios are varied or adjusted so that the compensation signal compensates the measured signal. In order to achieve this the value deviating from zero of the sum of the measured signal and the compensation signal is integrated, converted into digital values, and supplied to a PI-or PID-control circuit which controls in a closed loop manner the keying ratios of the square wave signals. The I-value of the PI- or PID-control circuit serves as a measure of the measured voltage.

Abstract: An up/down tracking counter stores a digital count signal equal to the time interval to be converted and provides this signal as the parallel digital output of the converter. Prior to the interval to be converted the count from the up/down counter is loaded into a down counter. At the leading edge of the interval to be converted the down counter is counted down, from the count loaded therein, by a clock signal until the occurrence of the trailing edge of the interval. A decision PROM responsive to the output of the down counter provides a message signal in accordance with the residual error count remaining in the down counter. The message signal commands a bit pattern generator that applies pulse burst controllably to the count up input or count down input of the up/down counter in accordance with the error count in the down counter so as to tend to reduce the error count in the down counter to zero.

Abstract: An A/D conversion method including the steps of storing digital voltage values obtained through an A/D conversion of divided voltages obtained by dividing an analog voltage in a predetermined voltage range into a predetermined number of different dividing ratios by an A/D converter and digital data for calculating digital output data for the A/D conversion of an input voltage in combination with the digital voltage values in a memory, converting the input voltage into a corresponding digital input value through A/D conversion, deciding upon a voltage division including the digital input value among divisions demarcated by the digital voltage values by sequentially comparing the digital voltage values with the digital input value, deciding which of a pair of the digital voltage values demarcating the division selected through the prior decision is the approximate value of the digital input value, updating the divided voltage corresponding to the digital voltage value through A/D conversion to provide a represe

Abstract: An electronically commutated coaxial starter motor for use with internal combustion engines of the type including those utilized with lawn mowers, pumps, generators, automobiles and the like.

Abstract: The present invention provides a parallel or "flash" analog-to-digital converter circuit (A) including a plurality of voltage comparators (20a-20g) arranged in first and second sets (F and E) adapted for receiving separate analog input signals. A push-pull configuration is employed in providing the analog input signal to the comparators of the two sets. The analog inputs (22a-22d) of the comparators (20a-20d) in the first set are provided in input signal V.sub.1 and the analog inputs (22e-22g) of the comparators (20e-20g) in the second set are provided an input signal V.sub.2 of equal magnitude but opposite polarity. Different reference voltages are provided to the reference inputs (24a-24g) of the comparators by a series-connected resistor network (H). Two encoders (I and J) and an adder (K) are used to detect the number of output signals from the comparators in a similar logic state and provide a digital binary output signal corresponding to the number of such outputs.

Abstract: A process for performing binary-to-decimal conversion distinguishes between two major subdivisions of the information represented by the binary values and signifies the type of information for each value by a so-called attribute bit. The attribute bits for several binary values can be encoded into a single decimal digit while each binary value is itself converted to a reduced number of decimal digits.

Abstract: The velocity of a cage during a time interval from the start of deceleration to the stoppage of the cage is controlled by utilizing a velocity characteristic which changes depending upon the load condition or oil temperature of a hydraulic elevator, that is, a magnitude by which the velocity characteristic during the acceleration of the cage differs from a reference running characteristic. Thus, even when the load state or the oil temperature has changed, the operating period of time of the hydraulic elevator is shortened, so that a comfortable ride, energy saving, cost reduction etc. are attained.

Abstract: A digital-to-analog converter comprising a ladder circuit resistance network and switching means comprising p-channel and n-channel MOS transistors. The distortion of analog signals generated by non-linear characteristics of resistors fabricated using p-channel or n-channel materials in the semiconductor are improved by replacing an inverter element module of the ladder circuit with T-type inverter circuit element module, and adjusting the resistance value of both the side branches of the T-type circuit.

Abstract: An error correction circuit (16) corrects errors in the thermometer code (T.sub.1 -T.sub.7) developed by a parallel or "flash" analog-to-digital converter (10). The error correction circuit employs plural similar bit exchange modules (34) of which each includes a 2-input OR gate (46) having common inputs (48 and 50) that constitute the inputs of the bit exchange module. The output (52) of the AND gate and the output (54) of the OR gate constitute the outputs of the bit exchange module. The bit exchange modules receive the digital-to-analog converter thermometer code and are interconnected to correct errors therein resulting from the presence of more than one transition between different logic states for adjacent bits in the thermometer code. The error correction circuit manipulates the thermometer code bits to provide a corrected thermometer code (T.sub.1C -T.sub.7C) that has only one transition between different logic states for adjacent bits thereof.

Abstract: A system for increasing the accuracy and resolution of an ADC comprising a digital filter connected to the output of the ADC, a system clock for providing a digital filter clock signal, a low/pass filter/amplifier for generating a large-scale, rapidly varying dither signal fdrom the digital filter clock signal, and a summing circuit for adding the dither signal to a test signal connected to the input of the ADC.

Abstract: A sequential decoding device for decoding a data expressed by a systematic code having a symbol memory, a maximum likelihood path decision circuit, and a path memory, includes: an overflow detection circuit for detecting an overflow of the symbol memory, and a switch for supplying signal bit data, as an decoded output, read from the symbol memory directly to the path memory in correspondence with an overflow detection signal from the overflow detection circuit. The device includes further a path metric value increase/decrease monitoring circuit for monitoring the increase/decrease of a path metric value delivered from the maximum likelihood path decision circuit and controlling the switch in such a manner that, when a monotonous increase of path metric value is detected, the decoded output of the maximum likelihood path decision circuit is supplied to the path memory instead of a direct supply of the decoded output of the symbol memory to the path memory.

Abstract: A method for adjusting capacitances in a monolithic integrated circuit wherein it is desirable that the capacitances form a binarily-weighted sequence of values includes sequentially-connecting trim capacitors in parallel with a primary capacitor and determining as each trim capacitor is connected, whether the resultant parallel capacitance is larger or smaller than that of a reference capacitance. If the resultant capacitance is too large, the trim capacitor is disconnected, but otherwise is left connected. The process is repeated until each trim capacitor has been tried. For the purpose of adjusting the capacitance of the next-largest capacitance, the final resultant capacitance is connected in parallel with the reference capacitance to form a new reference capacitance. The procedure is then repeated with the next-largest primary capacitor until the final resultant capacitance associated with each primary capacitor has been adjusted.

Abstract: A control circuit of a direct current servomotor which constantly rotates a floppy disk. A drive pin is connected to a motor shaft of the direct current servomotor, and the floppy disk is driven to rotate at a such state that engagement of the drive pin with a drive hole of the floppy disk chucks up the floppy disk on the servomotor. The direct current servomotor consists of a brushless motor that hall devices detect its magnet pole position and choose among the excited phases of the stator coils. The motor rotates to the reverse direction at the start-up by means of inversion of the input electric current flow to the hall devices in a short while and change-over of the magnet pole detecting direction. The reverse rotation at the motor start-up moves the drive pin on to the rear end of the drive hole, and the subsequent normal rotation firmly starts up the motor.

Abstract: An oversampling converter includes first and second integrators for integrating a difference between an input terminal voltage and feedback voltages, first and second quantizers for quantizing outputs from the first and second integrators, respectively, first and second feedback paths for feeding back as the feedback voltages outputs from the first quantizer to the input sides of the first and second integrators, a differentiator arranged at an output side of the second quantizer, an adder for adding an output from the differentiator and the output from the first quantizer, and a circuit for supplying an output from the first integrator to an input terminal of the second integrator. Two or more quantization loops may be used. When the oversampling converter is used as an A/D converter, A/D converters are arranged in the first and second feedback paths.

Abstract: In view of the limited speed times accuracy product of A-to-D and D-to-A converters, a required digital accuracy or sufficiently smooth analogue waveform cannot always be obtained. The present invention is useful in enhancing available converters. In the A-to-D version a stepped interpolation waveform obtained from a generator 13 is added to samples of an analogue waveform obtained from a sample-and-hold circuit 11 at a frequency 2f.sub.B (where f.sub.B is the bandwidth of the input signal). The resultant signal is applied to an n-bit A-to-D converter 15 operating at 2.sup.m times 2f.sub.B and the converter output is averaged using an accumulator 16 reset at 2f.sub.B. The accumulator output is a higher accuracy signal since it has m+n bits. An analogous technique is described for D-to-A conversion.

Abstract: Apparatus is disclosed which is controlled via computer interface logic for converting digital signals corresponding to predetermined synchro/resolver shaft angles into analog signals for stimulus purposes, and for converting the analog signals into digital words for measurement purposes. External synchro/resolver shaft angle signals may be converted into digital words for like purposes. The apparatus has a plurality of converter channels, each of which is controlled by the computer interface logic for operation independent of the other channels. The apparatus so configured is particularly adaptable for providing stimuli and measurements which are useful in test systems applications.