Abstract: A precipitation sensor for detecting when a predetermined fraction of the sensor area is covered with water drops comprises an insulating substrate, a pair of spaced electrodes of conductive material on the substrate, and an array of conductive spots on the substrate between the electrodes, the spots being arranged to define an open circuit between the electrodes when the substrate is dry and a closed circuit when at least some of the spots are bridged by water drops. This sensor uses the physical principle of percolation to respond accurately to small amounts of precipitation and is preferably integrated in the wipe area of a windshield surface and is incorporated in the wiper control system.

Abstract: There is provided an analog-to-digital conversion technique that utilizes a sample and hold circuit for each bit try stage whereby after the most significant bit try, the remainder is sampled and held by the succeeding stage as an unknown input voltage for comparison with its respective reference voltage representing its corresponding bit weight. Thus, remainders for each bit weight comparison are successively passed from the most significant bit to the least significant bit as input voltages to the next bit try stage. The previous bit stage takes a new sample input voltage and starts another conversion at the next clock pulse. After the first full digital output of the initial conversion, a new digital output word of the successive sampled signal voltage is available after each clock pulse.

Abstract: An analog/digital converter has an integrator for integrating for a predetermined time a difference voltage (<VX) between a voltage equal to half a source voltage V1 and an input voltage VX supplied to the first input terminal after an initialization period, generating an output voltage increasing in proportion to the input voltage, and generating an output voltage decreasing at a predetermined rate after the predetermined time has elapsed, and a counter for generating count data until the output voltage from the integrator reaches a predetermined level. This converter also has a resistor-type voltage divider and a capacitor. The voltage divider is coupled between source terminals and generating from first and second output terminals first and second output voltages E1 and E2 which are lower than voltage V1/2.

Abstract: The present invention relates to an electronic device that is used to calculate the actual torque being produced by an electric motor at any instant in time and comparing this value of torque ratiometrically either with the maximum (peak) torque that the motor could produce under the line voltage available at that instant or with rated motor torque, thus giving an indication of whether the motor is approaching stall or is under utilized or over utilized.

Abstract: A D/A/ converter for use in a microprocessor comprises first and second timers (3A, 3B), first and second modulus latches (2A, 2B) associated respectively with said first and second timers for holding respective digital values, the timers being arranged to produce first and second respective overflow signals (4A, 4B) at predetermined counts, wherein said second overflow signal (4B) causes said first and second timers (3A, 3B) to be reset to the digital values held in said respective latches (2A, 2B), and bistable means (6) for receiving said overflow signals and producing an output at a first level in response to said first overflow signal and at a second level in response to said second overflow signal, whereby the pulses so produced form a pulse width modulated signal whose duty cycle is representative of the ratio of said respective digital values held in said respective latches.

Abstract: A control system for an electronically commutated DC motor having a rotatable assembly and a stationary assembly with a plurality of winding stages. The application of a DC voltage to the winding stages is controlled to provide an effective voltage thereto by commutating the winding stages to apply the DC voltage thereto in sequence to cause rotation of the rotatable assembly. A neutral conductor voltage of the motor is approximated and compared with the back emf of one of the winding stages to obtain an output representing the angular position of the rotatable assembly. The winding stages are commutated in response to this output when a predetermined angular position is reached. The DC voltage applied to the winding stages is pulse width modulated by alternately pulse width modulating first and second drive circuits.

Abstract: An A/D converter comprising a multiplexer for selecting one of multi-channel analog signals sequentially, an A/D converting circuit for converting a selected analog signal into digital data, a memory for storing converted data in certain address locations, and a control circuit operating on the multiplexer to select an input and addressing the memory in unison in response to an external trigger signal.

Abstract: A terminal which is capable of receiving, converting and displaying both NAPLPS and PRESTEL coded signals and which includes means for invoking NAPLPS control and character codes, corresponding to the same, received PRESTEL codes, to an in-use table from NAPLPS code look-up tables at the terminal and for separately processing, decoding and converting PRESTEL attribute codes to produce corresponding NAPLPS codes.

Abstract: Method and apparatus which cyclically generate a compressed, arithmetically-coded binary stream in response to binary occurrence counts of symbols in an uncoded string. The symbols in the uncoded string are drawn from a multi-character alphabet which is not necessarily a binary one. Coding operations and hardware are simplified by deriving from the binary occurrence counts an estimate of the probability of each unencoded symbol at its precise lexical location. The probability estimation eliminates any requirement for division or multiplication by employing magnitude-shifting of the binary occurrence counts. The encoded stream is augmented by the estimated symbol probability at the same time that an internal variable is updated with an estimate of the portion of a probability interval remaining after coding the current symbol, the interval estimate being obtained from the left-shifted occurrence counts. Decoding is the dual of encoding.

Abstract: An oversampling type digital-to-analog converter which has a light gradient overload and a high signal-to-noise ratio in spite of a comparatively low sampling frequency.In a digital-to-analog converter wherein the difference between an oversampled digital input signal and a feedback signal is taken, such differences are integrated, the integral value is quantized to obtain the feedback signal, and part of the feedback signal is used as an analog output signal; a circuit for the quantization is constructed of a circuit which converts the integral value into a digital signal smaller in the number of bits than the digital input signal, and the feedback signal is obtained by integrating the outputs of the quantization circuit by means of a digital integral circuit.

Abstract: A narrow band signal is converted into digital form using an analogue to digital converter of relatively small capacity. The input signal is compared with a prediction of it based on previous cycles of the incoming waveform. This produces an error signal which is compared with a prediction of the error signal to produce an "error of the error" signal. A relatively small A/D converter converts this into 8 bit digital form and this is applied to a feedback loop consisting of an adder and delay to give a sixteen bit prediction of the error signal which is applied via D/A converter to the subtractor. The sixteen bit prediction also provides an input to a further adder forming part of a feedback loop to give an eighteen bit prediction of the input signal. The latter is applied via a D/A converter to a subtractor and is used as the system output.

Abstract: Phase information in a multiple-coil indictive displacement sensor is retained by summing the excitation signal with each of the secondary signals to provide augmented secondary signals which may then be converted to a digital format. A signal processor may then be employed to extract both the magnitude and phase information from the augmented secondary signals by subtracting the magnitude of the primary excitation signal from each of the augmented secondary signals. The resulting signals retain both phase and magnitude information.

Abstract: A signal sampling and conversion system for high-frequency sampling of either recurrent or non-recurrent signals in which the electron beam (9) generated by an electron gun (1) of a CRT is scanned across a target semiconductor integrated-circuit (4) comprising a linear array of tapered detection and storage elements in two opposing groups represented by elements (5an) and (5bn), connected respectively to parallel-to-serial convertors (7a) and (7b). The sampling rate is proportional to the scan rate which is determined by the scan signal (11) applied to the deflection electrodes (3). The input signal (10) applied to a high-frequency deflection structure (2) causes charges to be accumulated in the elements of the array which are indicative of the amplitude or range of amplitudes of the input signal (10) during the period of each sample. The charges are removed from the array and converted to serial output data (14a) and (14b) which may then be processed to yield the amplitude of the input signal.

Abstract: A method and apparatus for decoding a digital codeword of a codeword system comprising digital codewords of varying length in which no short codeword forms the prefix of a longer codeword in the same system comprises detecting with means (26) whether the codeword has a predetermined prefix, the predetermined prefix being shorter than any codeword containing it. Further means (26) are provided for decoding only the suffix of the codeword or the entire codeword respectively according to whether or not the predetermined prefix is detected.

Abstract: In order to reduce the numbers of resistors and associated switches required in a successive approximation type a-d converter, a resistor-ladder of the d-a converter utilizes a first group of resistors (resistance R) and a second group of resistors each having a resistance equal to R/2.sup.L wherein L is the number of lower bits of the digital output. The second group of resistors enables the generation of variable comparison reference signals in response to the output of a successive approximation register.

Abstract: A method and apparatus for compression of data includes first encoding data characters according to a relative frequency of use table for each character to produce a frequency code. This frequency code is then compressed using a modified Huffman code. The code is modified by restricting the maximum word length to a predetermined number of bits. Different types of text can be encoded according to different frequency of use tables to maximize compression efficiency for various types of source data with minimum data processing.

Abstract: An analog-to-digital converter quantizer and bidirectional counter using superconducting quantum interference devices (SQUID's) as the principal elements. A double-junction non-latching SQUID is used as a quantizer to produce unipolar output pulses on two different output lines, indicative of positive and negative increments of change in an analog signal current. The unipolar pulses are then counted in a bidirectional counter that employs double-junction non-latching SQUID's as counter stages and as logic gates for the propagation of carry and borrow signals from stage to stage.

Abstract: A system for converting an audio or like data signal from digital to analog form, with the addition of dither (white noise) to the digital input, with or without the subsequent removal of the dither from the analog output, for the reduction of quantization noise. Included is a network of n adders, equal in number to the n bits of the coded data signal, for adding in bit parallel form the digital data signal and the digital dither signal. Generated by an analog dither generator, the dither signal is transformed by an analog to digital converter into an m bit coded digital output, m being less than n, prior to delivery to the adder network. Some, preferably all, of the m bits of the digital dither signal are each added to, for example, two different ones of the n bits of the digital data signal so that, for instance, an eight bits analog to digital converter can be used for the provision of a digital dither signal to be added to a 16 bits digital audio signal.

Abstract: A control circuit is provided for a brushless three-phase d.c. motor which affords four quadrant control from a single command. The control circuit provides acceleration of the motor in both clockwise and counterclockwise directions and braking and generation in both clockwise and counterclockwise directions. In addition to turning on individual transistors of the transistor pairs connected to the phase windings of the motor for 120.degree. periods while the other transistor of that pair is off, the control circuit also provides, in a further mode of operation, turning the two transistors of each pair on and off alternately at a phase modulation frequency during such a 120.degree. period. A feedback signal is derived which is proportional to the motor current and which has a polarity consistent with the command signal, such that negative feedback results.

Abstract: A digital to analog converter circuit includes a current supply for providing a plurality of output currents of substantially equal magnitudes, a subtractor circuit coupled with selective outputs of the current supply for producing a plurality of binary weighted output currents and a summing circuit which is responsive to a binary coded digital input signal for selectively summing the binary weighted output currents and the remaining equal magnitude currents to provide a representative analog output current. The converter circuit is suited to be operated from a single source of power supply and does not require resistor trimming.