Abstract: A semiconductor package structure includes a conductive structure, at least two semiconductor elements and an encapsulant. The conductive structure has a first surface and a second surface opposite the first surface. The semiconductor elements are disposed on and electrically connected to the first surface of the conductive structure. The encapsulant covers the semiconductor elements and the first surface of the conductive structure. The encapsulant has a width ‘L’ and defines at least one notch portion. A minimum distance ‘d’ is between a bottom surface of the notch portion and the second surface of the conductive structure. The encapsulant has a Young's modulus ‘E’ and a rupture strength ‘Sr’, and L/(K×d)>E/Sr, wherein ‘K’ is a stress concentration factor with a value of greater than 1.2.

Abstract: This disclosure relates to a method for dissolving a silicon dioxide layer in a structure, including, from the back surface thereof to the front surface thereof, a supporting substrate, the silicon dioxide layer and a semiconductor layer, the dissolution method being implemented in a furnace in which structures are supported on a support, the dissolution method resulting in the diffusion of oxygen atoms included in the silicon dioxide layer through the semiconductor layer and generating volatile products, and the furnace including traps suitable for reacting with the volatile products, so as to reduce the concentration gradient of the volatile products parallel to the front surface of at least one structure.

Abstract: A transient voltage suppressor can include: a semiconductor substrate; a first buried layer of a first type formed in and on the semiconductor substrate; a second buried layer of a second type formed in a first region of the first buried layer; a first epitaxial region of the second type formed on the second buried layer and a second epitaxial region of the first type formed on a second region of the first buried layer; a first doped region of the first type formed in the first epitaxial region and a second doped region of the second type formed in the second epitaxial region; a conductive channel extending from a surface of the second epitaxial region into the first buried layer; and a first electrode connected to the conductive channel, a second electrode connected to the first doped region, and a third electrode connected to the second doped region.

Abstract: A method for packaging a microelectronic device in an hermetically sealed cavity and managing an atmosphere of the cavity with a dedicated hole, including making said cavity between a support and a cap layer such that a sacrificial material and the device are arranged in the cavity; removing the sacrificial material through at least one release hole, and hermetically sealing the release hole; making a portion of wettable material on the cap layer, around a blind hole or a part of said outside surface corresponding to a location of said dedicated hole; making a portion of fuse material on the portion of wettable material; making the dedicated hole by etching the cap layer; and reflowing the portion of fuse material with a controlled atmosphere, forming a bump of fuse material which hermetically plugs said dedicated hole.

Abstract: An organic electroluminescence display panel includes a substrate, an organic light-emitting layer disposed on the substrate, a first conductive pattern with a plurality of first meshes disposed on the substrate, a second conductive pattern with a plurality of second meshes disposed on the substrate and separated from the first conductive pattern, and a sealant dispensing area overlapped with the first conductive pattern and the second conductive pattern. A distance between two adjacent meshes of the first meshes is different from a distance between two adjacent meshes of the second meshes.

Abstract: A method of making a semiconductor device includes forming a first fin of a first transistor in a substrate; forming a second fin of a second transistor in the substrate; disposing a first doped oxide layer including a first dopant onto the first fin and the second fin, the first dopant being an n-type dopant or a p-type dopant; disposing a mask over the first fin and removing the first doped oxide layer from the second fin; removing the mask and disposing a second doped oxide layer onto the first doped oxide layer over the first doped oxide layer covering the first fin and directly onto the second fin, the second doped oxide layer including an n-type dopant or a p-type dopant that is different than the first dopant; and annealing to drive in the first dopant into a portion of the first fin and the second dopant into a portion of the second fin.

Abstract: A semiconductor package includes a suspended substrate having one or more semiconductor devices thereon, a metallic case covering the suspended substrate, the suspended substrate being supported by a plurality of mechanical leads on opposing sides of the semiconductor package, at least one of the plurality of mechanical leads having a coefficient of thermal expansion (CTE) that substantially matches a CTE of the suspended substrate, where at least one of the plurality of mechanical leads is electrically connected to the suspended substrate, and where the plurality of mechanical leads absorb mechanical shocks so as to prevent damage to the semiconductor package. The semiconductor package also includes a thermal gel between the suspended substrate and the metallic case. The suspended substrate can be a printed circuit board. The metallic case includes mounting ears for transferring heat away from the semiconductor package.

Abstract: Top-side cooling of Radio Frequency (RF) products in air cavity packages is provided. According to one aspect, an air cavity package comprises a substrate, a RF component mounted to the substrate, and a lid structure comprising a first material and being mounted to the substrate that covers the RF component such that a cavity is formed within the lid structure and about the RF component. At least one opening is provided in a top portion of the lid. The air cavity package also comprises a heat transfer structure comprising a second material and comprising a heat path extending from the top surface of the substrate through the opening(s) in the lid to the top outer surface of the air cavity package to provide a top-side thermal interface. In one embodiment, the lid is comprised of a molded material that absorbs RF signals and the heat transfer structure is metal.

Abstract: The present invention provides a method for forming a siliceous film. According to the method, a siliceous film having a hydrophilic surface can be formed from a polysilazane compound at a low temperature. In the method, a composition containing a polysilazane compound and a silica-conversion reaction accelerator is applied on a substrate surface to form a polysilazane film, and then a polysilazane film-treatment solution is applied thereon so that the polysilazane compound can be converted into a siliceous film at 300° C. or less. The polysilazane film-treatment solution contains a solvent, hydrogen peroxide and an alcohol.

Abstract: A power semiconductor module includes: a positive arm and a negative arm that are formed by series connection of self-arc-extinguishing type semiconductor elements, the positive arm and the negative arm being connected at a series connection point between the self-arc-extinguishing type semiconductor elements; a positive-side electrode, a negative-side electrode, and an AC electrode connected to the positive arm and the negative arm; and a substrate on which a plurality of wiring patterns are formed, the wiring patterns connecting the self-arc-extinguishing type semiconductor elements of the positive arm and the negative arm to the positive-side electrode, the negative-side electrode, and the AC electrode. Respective directions of current flowing in adjacent wiring patterns are identical to each other, and one of the adjacent wiring patterns is arranged in mirror symmetry with the other of the adjacent wiring patterns.

Abstract: Decrease of the output voltage of the logic circuit is inhibited by raising the gate voltage using a capacitor. In a first transistor, a drain and a gate are electrically connected to a first wiring, and a source is electrically connected to a first node. In a second transistor, a drain is electrically connected to the first node, a source is electrically connected to a second wiring, and a gate is electrically connected to a second node. In a third transistor, a drain is electrically connected to a third wiring, and a source is electrically connected to a third node, and a gate is electrically connected to the first node. In a fourth transistor, a drain is electrically connected to the third node, a source is electrically connected to a fourth wiring, and a gate is electrically connected to the second node. In a capacitor, one electrode is electrically connected to the first node, and the other electrode is electrically connected to the third node. OS transistors are preferably used as the transistors above.

Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a semiconductor nitride layer in contact with the semiconductor handle substrate, the semiconductor nitride layer selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof; a dielectric layer in contact with the semiconductor nitride layer; and a semiconductor device layer in contact with the dielectric layer.

Abstract: This application refers to a flip-chip structure of Group III semiconductor light emitting device. The flip-chip structure includes: a substrate, a buffer layer, nitride semiconductor layer, an active layer, a P type nitride semiconductor layer, a transparent conductive layer, a first insulation layer, a P type contact metal, a N type contact metal, a second insulation layer, a flip-chip P type electrode and a flip-chip N type electrode. The substrate, the buffer layer, the N type nitride semiconductor layer, the active layer, the P type nitride semiconductor layer which grow sequentially from bottom to top form a linear convex mesa. In this application, structure of the first insulation layer which is formed by aBraggs reflective layer, a metal layer and the multilayer oxide insulation layer, acts as a reflector structure and an insulation layer to replace the flip-chip reflector structure design and the first insulation layer, so that a metal protective layer can be omitted.

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor layer having a main surface, the main surface of the silicon carbide semiconductor layer being provided with a trench having a closed shape when seen in plan view, the trench including a bottom, a plurality of sidewalls continuous with the bottom, and a sidewall-connecting corner portion at a connection portion between two adjacent sidewalls of the plurality of sidewalls, the silicon carbide semiconductor device further including a gate insulating film covering the bottom and the sidewalls of the trench, and a gate electrode provided on the gate insulating film, between the bottom and an upper end of the trench, the thickness of the gate insulating film at the sidewall-connecting corner portion of the trench being greater than the thickness of the gate insulating film at a portion other than the sidewall-connecting corner portion.

Abstract: According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are stacked on a substrate. The semiconductor layer has one end connected to the substrate, has as its longer direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. Assuming at least one control gate electrode positioned in a lowermost layer of the plurality of control gate electrodes to be a first control gate electrode, the first control gate electrode comprises: a first portion; a second portion adjacent to the first portion; and a third portion connected to the first portion and the second portion.

Abstract: On-chip, three-dimensional MIM capacitors are provided. In one aspect, a method for forming a device includes: forming at least one MOSFET structure and at least one MIM capacitor structure on a substrate each structure including: a metal gate, and source and drain regions on opposite sides of the metal gate, and wherein the structures are buried in a dielectric; forming metal contacts in the dielectric down to the source and drain regions; forming a mask that selectively covers the MOSFET structure; removing the dielectric from uncovered portions of the MIM capacitor structure forming gaps between the metal contacts and the metal gate in the MIM capacitor structure; depositing a capacitor dielectric in the gaps; and depositing a fill metal onto the capacitor dielectric filling the gaps. A MIM capacitor and a device including an MIM capacitor are also provided.

Abstract: An organic layer deposition apparatus including: a conveying unit including a first conveying unit conveying in a first direction a moving unit to which a substrate is removably adhered, and a second conveying unit conveying in a direction opposite to the first direction the moving unit from which the substrate is separated, in which the moving unit may be cyclically conveyed by the first and second conveying units; and a deposition unit including a deposition assembly being separate from the substrate while the first conveying unit conveys the substrate adhered to the moving unit and having a material deposited onto the substrate, and a housing having the deposition assembly provided therein and an internal space allowing the moving unit to pass therethrough, in which the movable unit may include a main body unit, an electrostatic chuck provided on the main body unit and having the substrate adhered thereto, a contactless power supply (CPS) module provided facing with the electrostatic chuck each other on th

Abstract: The invention provides an optoelectronic semiconductor component and a method for producing an optoelectronic semiconductor component (10), comprising the following steps: A) arranging at least one semiconductor chip (2) on a carrier (1), B) applying an electrically insulating photoresist (3) to a top side (1a) of the carrier (1) and to the semiconductor chip (2), C) curing the photoresist (3) with a baking step, D) patterning the photoresist (3) by exposure, F) developing the photoresist (3), wherein the photoresist (3) is removed at least from a radiation penetration surface (2b) of the semiconductor chip (2), G) again curing the photoresist (3) with a baking step, and H) applying an electrically conductive contact layer (4) to the photoresist (3), wherein the electrically conductive contact layer (4) is in places at a distance (A) from a marginal surface (3a) of the photoresist (3) which faces towards the semiconductor chip (2), wherein the marginal surface (3a) facing towards the semiconductor chip (2) is

Abstract: A method of fabricating an integrated circuit includes forming a plurality of polysilicon gate electrode structures over a plurality of fin-shaped channel structures. A portion of the plurality of polysilicon gate electrode structures may then be removed to expose a surface region of a fin-shaped channel structure in the plurality of fin-shaped channel structures. The remaining portion of the polysilicon gate electrode structures may form a plurality of polysilicon transistors. A layer of high-k dielectric material is deposited on the exposed surface region of the fin-shaped channel structure. A metal layer may be deposited over the high-k dielectric material to form at least one high-k metal gate transistor over the fin-shaped channel structure.

Abstract: The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.