Patents Examined by Charles L. Bowers, Jr.
  • Patent number: 6190992
    Abstract: A method and apparatus for enhanced capacitance per unit area electrodes is utilized in semiconductor memory devices. The capacitance is enhanced by roughening the surface of the bottom electrode in such devices. In one embodiment of the invention, surface roughness is achieved on a polysilicon bottom capacitor electrode by depositing doped polysilicon on the outside surfaces of a bottom capacitor electrode and vacuum annealing. In another embodiment of the invention, surface roughness is achieved by depositing a GeO2-embedded GeBPSG layer on a substrate, annealing, selectively etching to remove GeO2, forming a container, and depositing a blanket rough polysilicon layer over the GeBPSG layer to replicate the underlying surface roughness.
    Type: Grant
    Filed: July 15, 1996
    Date of Patent: February 20, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Singh Sandhu, Randhir P. S. Thakur
  • Patent number: 6124153
    Abstract: A method for manufacturing a polysilicon thin film transistor (TFT) according to the present invention reduces the electric field near the drain junction by varying partially the thickness of a gate insulating layer through a post oxide process. A polysilicon layer is patterned to become an active layer and a chemical vapor deposition oxide film deposited. By thermal oxidation a thermal oxide film is formed under the chemical vapor deposition oxide film. A gate electrode made of polysilicon is formed on the gate insulating layer. Thermal oxidation is performed to make the end portions of the thermal oxide film thicker than the portion under the gate electrode of the thermal oxide film. With this process, the electric field near the drain junction region is reduced and thus the leakage currents of the TFT decrease. In addition, the method in this invention is very simple compared with the conventional methods of obtaining a LDD structure and on-current is not reduced.
    Type: Grant
    Filed: July 15, 1996
    Date of Patent: September 26, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-hyung Lee, Yong-suk Jin
  • Patent number: 6062869
    Abstract: A stacked film assembly for use as wiring in a semiconductor device having a bottom film (CVD-W film) 33 and a top film (Al alloy film) 12, where the surface roughness (Ra) of the bottom film is less than 100 .ANG. and the crystal orientation of the top film formed on this surface is controlled, a CVD method for the making thereof, and a semiconductor device in which the stacked film assembly is employed. Even when there is no lattice matching of the bottom film and the top film, crystal orientation of the top film can be sufficiently controlled to provide a targeted face ((111) face with aluminum film), and in particular it will be possible to readily form a stacked film assembly having a satisfactory barrier function as well as sufficient EM resistance and with good film formation.
    Type: Grant
    Filed: September 26, 1994
    Date of Patent: May 16, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Koichi Mizobuchi, Toshihiro Sugiura
  • Patent number: 6054396
    Abstract: A semiconductor processing method of reducing thickness depletion of a nitride layer at a junction of different underlying layers includes, a) providing a substrate, the substrate comprising a first material and a second material, the first and second materials joining at a surface junction, the first and second materials being different from one another; b) exposing the substrate to a nitrogen containing gas under pressure and elevated temperature conditions effective to nitridize an outer portion of both the first and second materials with the nitrogen containing gas to provide a nitrogen containing nucleation layer at the outer portion of both of the first and second materials over the surface junction; and c) chemical vapor depositing a nitride layer atop the nucleation layer over the first and second materials and the surface junction.
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: April 25, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Trung Tri Doan
  • Patent number: 6033928
    Abstract: On a silicon substrate is formed a silicon dioxide film and then hemispherical grains made of silicon, each having an extremely small diameter, are deposited thereon by LPCVD. After annealing the hemispherical grains, the silicon dioxide film is etched using the hemispherical grains as a first dotted mask, thereby forming a second dotted mask composed of the silicon dioxide film. The resulting second dotted mask is used to etch the silicon substrate to a specified depth from the surface thereof, thereby forming an aggregate of semiconductor micro-needles. Since the diameter of each of the semiconductor micro-needles is sufficiently small to cause the quantum size effects as well as has only small size variations, remarkable quantum size effects can be obtained. Therefore, it becomes possible to constitute a semiconductor apparatus with a high information-processing function by using the aggregate of semiconductor micro-needles (quantized region).
    Type: Grant
    Filed: November 2, 1994
    Date of Patent: March 7, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Eriguchi, Masafumi Kubota, Masaaki Niwa, Noboru Nomura
  • Patent number: 6022766
    Abstract: An improved field effect transistor (FET) structure is disclosed. It comprises a first insulator layer containing at least one primary level stud extending through the layer; an undoped cap oxide layer disposed over the insulator layer and abutting the upper region of each stud; a primary level thin film transistor (TFT) disposed over the undoped cap oxide layer; and a planarized oxide layer disposed over the TFT. Multiple TFT's can be stacked vertically, and connected to other levels of studs and metal interconnection layers. Another embodiment of the invention includes the use of a protective interfacial cap over the surface of tungsten-type studs. The FET structure can serve as a component of a static random access memory (SRAM) cell. Related processes are also disclosed.
    Type: Grant
    Filed: February 10, 1997
    Date of Patent: February 8, 2000
    Assignee: International Business Machines, Inc.
    Inventors: Bomy Able Chen, Subhash Balakrishna Kulkarni, Jerome Brett Lasky, Randy William Mann, Edward Joseph Nowak, Werner Alois Rausch, Francis Roger White
  • Patent number: 6001551
    Abstract: A silver halide color light-sensitive material containing a cyan coupler which provides an excellent hue and an improved fastness at a low color-developing area and which has small change in a color developing density, which is caused by change of a composition of a blix solution and provides a small fog in a cyan color at a non-exposed area in a continuous processing. The silver halide color light-sensitive material contains at least one cyan coupler represented by the following Formula (I) in at least one layer on a support: wherein Y represents --N.dbd. or --C(R.sub.3).dbd.; X represents a hydrogen atom or a group which splits off upon a coupling reaction with an oxidized product of a color developing agent; Z represents a non-metallic atomic group necessary for forming an alicyclic group or a heterocyclic ring; R.sub.1, R.sub.2 and R.sub.3 each represents a hydrogen atom or a substituent; and R.sub.
    Type: Grant
    Filed: November 16, 1994
    Date of Patent: December 14, 1999
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Yasuhiro Shimada, Koushin Matsuoka, Hiroyuki Yoneyama
  • Patent number: 5975912
    Abstract: Using plasma enhanced chemical vapor deposition, various layers can be deposited on semiconductor substrates at low temperatures in the same reactor. When a titanium nitride film is required, a titanium film can be initially deposited using a plasma enhanced chemical vapor deposition wherein the plasma is created within 25 mm of the substrate surface, supplying a uniform plasma across the surface. The deposited film can be subjected to an ammonia anneal, again using a plasma of ammonia created within 25 mm of the substrate surface, followed by the plasma enhanced chemical vapor deposition of titanium nitride by creating a plasma of titanium tetrachloride and ammonia within 25 mm of the substrate surface. This permits deposition film and annealing at relatively low temperatures--less than 800.degree. C.
    Type: Grant
    Filed: June 3, 1994
    Date of Patent: November 2, 1999
    Assignees: Materials Research Corporation, Sony Corp.
    Inventors: Joseph T. Hillman, Robert F. Foster
  • Patent number: 5955786
    Abstract: A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After the formation of the void in the 0.5 microns or less gaps, the deposition of the nonconformal source material is stopped and a flowable insulating material, such as spin on glass, is coated on nonconformal insulating material to fill the remaining gaps. After etching the surfaces of the nonconformal and flowable insulating materials, another insulating layer is deposited and planarized to the desired overall thickness of the insulation. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: September 21, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Steven Avanzino, Darrell Erb, Robin Cheung, Rich Klein
  • Patent number: 5956592
    Abstract: A method of manufacturing a semiconductor device by forming first and second resistor layers of polycrystalline silicon including impurities on a first insulation film with a predetermined distance therebetween. The resistor layer have a resistance ratio set to a predetermined value. A second insulation film is formed on the first and second resistor layers and has an opening in a predetermined region. A metal layer electrically connected to the first and second resistor layers is formed in the opening and extends onto the second insulation film. The metal layer is patterned to form a first metal interconnection layer electrically connected to the first resistor layer and a second metal interconnection layer electrically connected to the second resistor layer. The first metal interconnection layer partially covers the first resistor layer. The second metal interconnection layer partially covers the second resistor layer.
    Type: Grant
    Filed: January 22, 1996
    Date of Patent: September 21, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Masaaki Ikegami
  • Patent number: 5939333
    Abstract: A silicon nitride deposition method includes providing a substrate surface including one or more component surfaces. At least a monolayer of silicon is predeposited on the one or more component surfaces of the substrate surface resulting in a substantially native oxide free uniform predeposited silicon substrate surface. Thereafter, a silicon nitride layer is deposited on the predeposited silicon substrate surface after the silicon predeposition. Further, another silicon nitride deposition method includes providing a silicon based substrate surface. The substrate surface is nitridated in an atmosphere of dimethylhydrazine, and thereafter, a silicon nitride layer is deposited on the nitridated surface. The nitridation of the substrate surface results in a thickness less than three monolayers of silicon nitride.
    Type: Grant
    Filed: May 30, 1996
    Date of Patent: August 17, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Kelly T. Hurley, Li Li, Pierre Fazan, Zhiqiang Wu
  • Patent number: 5923962
    Abstract: A process for fabricating a highly stable and reliable semiconductor, comprising: coating the surface of an amorphous silicon film with a solution containing a catalyst element capable of accelerating the crystallization of the amorphous silicon film, and heat treating the amorphous silicon film thereafter to crystallize the film.
    Type: Grant
    Filed: April 28, 1995
    Date of Patent: July 13, 1999
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Akiharu Miyanaga, Takeshi Fukunaga, Hongyong Zhang
  • Patent number: 5904513
    Abstract: A thin film transistor includes: a) a thin film transistor layer comprising a source region, a channel region and a drain region; the thin film transistor layer further comprising a drain offset region positioned between the drain region and the channel region; b) the channel region being substantially polycrystalline and having a first average crystalline grain size; and c) the drain offset region being substantially polycrystalline and having a second average crystalline grain size, the second average crystalline grain size being larger than the first average crystalline grain size. A method for forming such a construction using polycrystalline materials, preferably polysilicon, and an amorphizing silicon implant with subsequent recrystallization is also disclosed.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: May 18, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Shubneesh Batra, Monte Manning, Sanjay Banerjee, John Damiano, Jr.
  • Patent number: 5905044
    Abstract: A mass manufacturing method of semiconductor acceleration and vibration sensors uses a dispensing method, a electrical plating method, a screen-printing method or a preforming method in manufacturing a mass made of metal pastes in a desired size and amount on a mass pad of a thin metal film which is formed on a beam in a given pattern, so that it can be adapted to the mass-production of the sensors having the mass of the desired amount and size.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: May 18, 1999
    Assignees: Kyungpook National University Technology Research Center, Mando Machinery Corporation
    Inventors: Jong Hyun Lee, Woo Jeong Kim
  • Patent number: 5902122
    Abstract: A method of manufacturing a semiconductor device is provided. A first interlayer insulating layer is formed on a silicon substrate, and a lower metal layer is formed on the first interlayer insulating layer. A first insulating layer is formed on the first interlayer insulating layer including the lower metal layer, moisture contained in the first insulating layer is removed by N.sub.2 or N.sub.2 O plasma. Thereafter, a SOG layer and a second insulating layer are sequentially formed on the first insulating layer.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: May 11, 1999
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Dong Sun Sheen, Jeong Rae Lee
  • Patent number: 5893745
    Abstract: Methods of forming semiconductor-on-insulator field effect transistors include the steps of forming an insulated trench containing a semiconductor region therein and an insulating region mesa at a bottom of the trench, so that the semiconductor region has relatively thick regions adjacent the sidewalls of the trench and has a relatively thin region above the mesa. Dopants can then be added to the thick regions to form low resistance source and drain regions on opposite sides of the thin region which acts as the channel region. Because the channel region is thin, low junction capacitance can also be achieved. An insulated gate electrode can also be formed on the face of the semiconductor region, above the channel region, and then source and drain contacts can be formed to the source and drain regions to complete the device.
    Type: Grant
    Filed: June 13, 1996
    Date of Patent: April 13, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyu-charn Park
  • Patent number: 5893721
    Abstract: A method of fabricating an active matrix LED array includes forming layers of material on a substrate, which layers cooperate to emit light when activated. Row and column dividers are formed in the layers to divide the layers into an array of LEDs arranged in rows and columns. One FET is formed on the row dividers in association with each LED and a source of each FET is connected to an anode of the associated LED. Row and column buses are formed on the row and column dividers, respectively, and the drain of each FET is connected to an adjacent row bus with the gate of each FET being connected to an adjacent column bus. A cathode for each LED is connected as a common terminal for all of the LEDs in the array.
    Type: Grant
    Filed: March 24, 1997
    Date of Patent: April 13, 1999
    Assignee: Motorola, Inc.
    Inventors: Rong-Ting Huang, Phil Wright, Paige M. Holm
  • Patent number: 5893722
    Abstract: A vertical cavity surface emitting laser having a planar structure, having an implantation or diffusion at the top of the mirror closest to the substrate or at the bottom of the mirror farthest from the substrate, to provide current confinement with the gain region, and having an active region and another mirror formed subsequent to the implantation or diffusion. This structure has an implantation or diffusion that does not damage or detrimentally affect the gain region, and does provide dimensions of current confinement that are accurately ascertained. Alternatively, the implantation or diffusion for current confinement may be placed within the top mirror, and several layers above the active region, still with minimal damage to the gain region and having a well-ascertained current confinement dimension.
    Type: Grant
    Filed: April 28, 1997
    Date of Patent: April 13, 1999
    Assignee: Honeywell Inc.
    Inventors: Mary K. Hibbs-Brenner, James R. Biard
  • Patent number: 5891748
    Abstract: On an n-InP substrate (101), a mask (102) having a first portion (102a) and a second portion (102b) is formed. The mask (102) has a first gap (NG) at the first portion (102a). A width of the second portion (102b) is greater than a width of the first portion (102a). A core layer (120) is epitaxially grown selectively on the substrate (101) at an area corresponding to the first gap (NG). The first gap (NG) is widened and an additional gap (AG) is formed at the second portion (102b) to form a second gap (WG) comprising the first gap after widened and the additional gap (AG). A clad layer (106) is epitaxially grown on the substrate (101) at an area corresponding to the second gap (WG) so as to cover the core layer(120). A difference in width between the first portion (102a) and the second portion (102b) is set so that a thickness of the clad layer at an area corresponding to the second portion (102b) becomes equal to a thickness of the clad layer (106) at an area corresponding to the first portion (102a).
    Type: Grant
    Filed: May 13, 1997
    Date of Patent: April 6, 1999
    Assignee: NEC Corporation
    Inventor: Yasutaka Sakata
  • Patent number: 5891743
    Abstract: A method of manufacturing a wafer having a buried oxide layer at a desired depth is disclosed. The method includes the steps of implanting a standard species ion at an energy at or above 1 MeV into an oxygen-rich wafer to form a defect region at the desired depth in the oxygen rich wafer. The wafer is annealed such that oxygen in the wafer is gettered to the defect region to form the buried oxide layer.
    Type: Grant
    Filed: December 24, 1996
    Date of Patent: April 6, 1999
    Assignee: Advanced Micro Device Inc.
    Inventor: John K. Lowell