Abstract: A thin-film transistor structure having a storage-capacitor-on-gate and a black matrix for manufacturing a liquid crystal display is disclosed. A metal layer is deposited and patterned as a black matrix on a glass substrate of the thin-film transistor plate. An insulating layer having a contact hole for contacting the black matrix is formed over the surface of the black matrix and the substrate. An inverted thin-film transistor having a metal gate on the bottom is then fabricated on top of the insulating layer. The thin-film transistor controls an ITO pixel electrode of the liquid crystal display. A gate line including the metal gate of the thin-film transistor is formed over and above a space between two adjacent black matrixes. The gate line is connected to one of the two black matrixes by the contact hole. The other black matrix serves as a light shield element of the ITO pixel electrode.

Abstract: Using a nickel element which is a metal element for promoting crystallized of silicon, an amorphous silicon film is crystallization into a crystalline silicon film, and then a thin film transistor (TFT) is produced by using the crystalline silicon film. That is, a solution containing nickel (for example nickel acetate solution) which promotes crystallization of silicon is applied in contact with a surface of an amorphous silicon through the spin coat method. Then the heating treatment is performed to crystallize the amorphous silicon film into the crystalline silicon film. In the state, nickel silicide components are removed using a solution containing hydrofluoric acid, hydrogen peroxide and water.

Abstract: A stacked capacitor of a DRAM cell has an increased storage electrode without increasing the total area and fabrication complexity of the DRAM cell. By disposing the storage electrode of a memory capacitor on an especially made rugged stacked oxide layer, the area of the storage electrode is enlarged and thus provides the higher capacitance. Then, by removing the rugged stacked oxide layer to expose the rugged surface of the storage electrode, the capacitance of a memory capacitor is additionally increased after covering the whole rugged surface of a of the storage electrode with a dielectric film.

Abstract: A new technique for the formation of high quality ultrathin gate dielectrics is proposed. Gate oxynitride was first grown in N.sub.2 O and then annealed by in-situ rapid thermal NO-nitridation. This approach has the advantage of providing a tighter nitrogen distribution and a higher nitrogen accumulation at or near the Si--SiO.sub.2 interface than either N.sub.2 O oxynitride or nitridation of SiO.sub.2 in the NO ambient. It is applicable to a wide range of oxide thickness because the initial rapid thermal N.sub.2 O oxidation rate is slow but not as self-limited as NO oxidation. The resulting gate dielectrics have reduced charge trapping, lower stress-induced leakage current and significant resistance to interface state generation under electrical stress.

Abstract: A method for forming a dielectric layer on a surface of a substrate uses high pressure. A pressure vessel of a high pressure oxidation equipment is heated to a predetermined temperature. The substrate is placed inside the pressure vessel. The pressure vessel is pressurized to a pressure above atmospheric pressure. A flow of an oxidizing gas and a flow of steam are introduced into the pressure vessel, wherein the steam flow is only a fraction of the oxidizing gas flow. The dielectric layer on the surface is formed through an oxidizing reaction of the oxidizing gas and steam with the surface of the substrate, wherein the flow of steam acts in a catalytic-like manner to parabolicly accelerate the oxidizing reaction at the surface.

Abstract: A method is provided for making conductive structures whereby an insulating layer is formed over a substrate. A conductive layer is then formed over the insulating layer. A first photoresist layer is formed over the conductive layer, patterned and developed. The conductive layer is etched after which the first photoresist layer is removed. A second photoresist layer is formed over the integrated circuit, patterned and developed. The remaining regions of the conductive layer forming an interconnect or a gate are partially etched to form two-tiered stepped sidewalls.

Abstract: A wiring structure of a semiconductor device includes a substrate; a first conductive layer formed in the substrate; an insulation film formed on the substrate including the first conductive layer and having a contact hole therein through which the upper surface of the first conductive layer is exposed, wherein the contact hole includes an upper contact hole and a lower contact hole having a shape undercut into the insulation film and thus being wider than the upper contact hole; and a second conductive layer formed on the insulation film so as to thoroughly fill the contact hole and electrically connected to the first conductive layer.

Abstract: A wafer processing method relates to treating a semi-conductor wafer and in particular, but not exclusively, to planarization. The method consists of depositing a liquid short-chain polymer formed from a silicon containing gas or vapor. Subsequently water and OH are removed and the layer is stabilised.

Abstract: A method for forming a capacitor having HSG polysilicon with reduced dielectric bridging, increased capacitance, and minimal depletion effects. A first polysilicon layer is deposited and doped with impurities to increase conductivity. A second polysilicon layer is LO deposited at a temperature adjusted to cause a nucleation of the second polysilicon layer. As a result of the nucleation the second polysilicon layer is altered to resemble hemispherical grains. Next the first and second polysilicon layers are oxidized in an oxide/phosphine ambient. During the oxidation portions of the first and second polysilicon layers are consumed forming a phosphine rich oxygen layer on the surface of the hemispherical grains and in portions of the first polysilicon layer lying between the grains which are reduced in size due to the oxidation. A wet etch is then performed to remove the oxygen layer. Phosphorous ions are driven into the hemispherical grains during the oxidation thereby doping the grains.

Abstract: A planarization process for filling spaces between patterned metal features formed over a surface of a semiconductor substrate. The patterned metal features are preferably coated with a dielectric barrier. The dielectric barrier is coated with an material that expands during oxidation or nitridization to a thickness about half the depth of the space between metallized features. The layer is then plasma oxidized using an RF or ECR plasma at low temperature with an oxygen ambient. Alternatively, the layer is plasma nitridized at low temperature. The plasma oxidation or nitridization is continued until the expandable material is converted to a dielectric and has expanded to fill the space between patterned metal features. Optionally, the process can be followed by a mechanical or chemical mechanical planarization step.

Abstract: An Si--O--F insulating film having a low dielectric constant is deposited on a substrate by thermally reacting disassociated SiF.sub.4 radicals and ozone or oxygen gas in a vacuum chamber. The SiF.sub.4 radicals are formed remotely from the chamber and interact thermally with the ozone or oxygen without requiring plasma enhancement. The deposited Si--O--F film has good gap-filling properties and is suitable for forming IMD layers over high aspect ratio 0.25 micron geometries.

Abstract: Values of a real part n and an imaginary part k of the relation indicating a complex refractive index as an optical characteristic of an anti-reflection film are selected to be in the ranges of 1.0<n<3.0 and 0.4<k<1.3, respectively. The values of the real part and n and the imaginary part k of the complex refractive index are set in the above-described range by changing parameters of composition of a material of a plasma nitride film formed by a plasma CVD method. By this method, it is possible to easily select the anti-reflection film having an optimum optical characteristic without depending on experiments.

Abstract: Optoelectronic devices such as photodetectors, modulators and lasers with improved optical properties are provided with an atomically smooth transition between the buried conductive layer and quantum-well-diode-containing intrinsic region of a p-i-n structure. The buried conductive layer is grown on an underlying substrate utilizing a surfactant-assisted growth technique. The dopant and dopant concentration are selected, as a function of the thickness of the conductive layer to be formed, so that a surface impurity concentration of from 0.1 to 1 monolayer of dopant atoms is provided. The presence of the impurities promotes atomic ordering at the interface between the conductive layer and the intrinsic region, and subsequently results in sharp barriers between the alternating layers comprising the quantum-well-diodes of the intrinsic layer.

Abstract: A method for forming within a Field Effect Transistor (FET) for use within an integrated circuit a polycide gate electrode. There is first provided a semiconductor substrate. Formed upon the semiconductor is a patterned polysilicon layer. Formed then upon the semiconductor substrate and the patterned polysilicon layer is a blanket insulator layer. The blanket insulator layer is then patterned through planarizing to form a patterned planarized insulator layer while simultaneously exposing the surface of the patterned polysilicon layer. Finally, there is formed upon the exposed surface of the patterned polysilicon layer a patterned metal silicide layer. The patterned metal silicide layer and the patterned polysilicon layer form a polycide gate electrode. The metal silicide layer within the polycide gate electrode is not susceptible to encroachment upon adjoining insulator spacers or source/drain regions within the Field Effect Transistor (FET) within which is formed the polycide gate electrode.

Abstract: At least both a rapid thermal etch step and a rapid thermal oxidation step are performed on a semiconductor substrate in situ in a rapid thermal processor. A method including an oxidation step followed by an etch step may be used to remove contamination and damage from a substrate. A method including a first etch step followed by an oxidation step and a second etch step may likewise be used to remove contamination and damage, and a final oxidation step may optionally be included to grow an oxide film. A method including an etch step followed by an oxidation step may also be used to grow an oxide film. Repeated alternate in situ oxidation and etch steps may be used until a desired removal of contamination or silicon damage is accomplished.

Abstract: An integrated process for forming a 4T SRAM and a mixed-mode capacitor, with logic, on the same integrated circuit, is provided. A semiconductor substrate is provided having field isolation regions, with a gate and gate oxide between the field isolation regions. Polysilicon interconnects are formed over a portion of the field isolation regions, only in a first memory region, and a bottom capacitor plate over a field oxide region in a capacitor region. Active regions are formed in the substrate, adjacent to each gate. Insulating spacers are formed on the sidewalls of the gates, polysilicon interconnects and the floating gate, and later removed from the interconnect. A layer of titanium silicide is formed over the gates and capacitor bottom plate, and also over the polysilicon interconnects and active regions. An interpoly oxide is formed over the semiconductor substrate. An opening is formed in the interpoly oxide over the polysilicon interconnect. A second layer of polysilicon is deposited over the substrate.

Abstract: A process for making multiple microelectronic ceramic substrates uses an interface layer between stacked layers of green sheets that are laminated with the interface layer, then fired to produce the ceramic substrates. The interface layer acts to protect the substrates, and to hold them together before firing, then thermally degrades at a desired point in the firing cycle to separate the individual substrates. The invention also includes the ceramic substrates produced by the method.

Abstract: A method of depositing a Group IIIA metal layer of high purity on a substrate comprises pyrolyzing contacting the substrate with a tritertiary butyl compound of the Group IIIA metal and pyrolyzing the compound to leave the Group IIIA metal deposited on the substrate. The method of the invention may be used on any suitable substrate, such as silicon or polyimide. The method of the invention may be used for the growth of Group IIIA/silicon alloys as well as for depositing semi-conducting III-V alloys such as, for example, AlGaAs, AlInAs and AlSb.

Abstract: The present invention provides an interconnect system. The interconnect system includes a substrate, a first dielectric layer deposited upon the substrate. The interconnect system further includes at least two electrically conductive interconnect lines formed upon the first dielectric layer. Each of the at least two interconnect lines have a top surface and side surfaces. Adjacent side surfaces of two adjacent interconnect lines define therebetween a space that has a dielectric constant substantially equal to 1. A dielectric film is bonded upon the top surface of the at least two interconnect lines. The dielectric film substantially prevents obstruction of the space by further process.

Abstract: A wafer holder for maintaining a semiconductor wafer at a constant temperature during film deposition is disclosed. The wafer holder is configured to have one or more quartz arms. Affixed to each arm is at least one quartz support, whose top end is adapted for holding the semiconductor wafer. The top end of each support is tapered to have a diameter smaller than that of the quartz support and is optionally tapered to a point. A thermal mass element is optionally supported on the arms of the wafer holder, to keep uniform, the temperature at the perimeter of the wafer with respect to the rest of the semiconductor wafer during a material layer deposition. Also, a quartz backstop is optionally attached to each support arm to keep the semiconductor wafer positioned on top of the quartz supports when the wafer holder is rotated.