Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together through at least one other interconnect level.

Abstract: A semiconductor layout structure includes a substrate comprising a cell edge region and a dummy region abutting thereto, a plurality of dummy contact patterns disposed in the dummy region and arranged along a first direction, and a plurality of dummy gate patterns disposed in the dummy region and arranged along the first direction. The dummy contact patterns and the dummy gate patterns are alternately arranged. Each dummy contact pattern includes an inner dummy contact proximal to the cell edge region and an outer dummy contact distal to the cell edge region, and the inner dummy contact and the outer dummy contact are arranged along a second direction perpendicular to the first direction and spaced apart from each other by a first gap.

Abstract: A light emitting device includes an electrode layer, a first metal layer, an organic material layer and a second metal layer stacked sequentially. The first metal layer includes a first metal portion and a second metal portion separated from the first metal portion at a first lateral distance, and the first metal portion and the second metal portion have a first period. The organic material layer includes a first emitting region separating the first metal portion and the second metal portion. The first lateral distance and the first period enable a lateral plasma coupling generated between the first metal portion and the second metal portion, such that light generated by the organic material layer at the first emitting region has a gain in a first waveband, or a peak wavelength of the light generated by the first emitting region shifts to the first waveband.

Abstract: A transistor device includes a compound semiconductor body, a drain disposed in the compound semiconductor body and a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region. A gate is provided for controlling the channel region. The transistor device further includes a gate overvoltage protection device connected between the source and the gate, the gate overvoltage protection device including p-type and n-type silicon-containing semiconductor material.

Abstract: A semiconductor structure includes: a germanium layer; and a first insulating film that is formed on an upper surface of the germanium layer, primarily contains germanium oxide and a substance having an oxygen potential lower than an oxygen potential of germanium oxide, and has a physical film thickness of 3 nm or less; wherein a half width of frequency to height in a 1 ?m square area of the upper surface of the germanium layer is 0.7 nm or less.

Abstract: A semiconductor device includes a source including a first doped semiconductor layer arranged on a substrate, a layer of metal arranged on the first doped semiconductor layer, and a second doped semiconductor layer arranged on the layer of metal; a channel extending from the second doped semiconductor layer to a drain including an epitaxial growth; a gate disposed on sidewalls of the channel between the second doped semiconductor layer and the drain; an interlayer dielectric (ILD) disposed on the second doped semiconductor layer and the gate; and a source contact extending from a surface of the ILD to abut the layer of metal of the source.

Abstract: The present application discloses a semiconductor device comprising a crystalline substrate having a first region and a second region, a nuclei structure on the first region, a first crystalline buffer layer on the nuclei structure, a void between the second region and the first crystalline buffer layer, a second crystalline buffer layer on the first crystalline buffer layer, an intermediate layer located between the first crystalline buffer layer and the second crystalline buffer layer, and a semiconductor device layer on the second crystalline buffer layer.

Abstract: According to one aspect, the present invention concerns a terahertz modulator (1) intended to be used in a given frequency band of use. The modulator comprises a semi-conductor polar crystal (330) presenting a Reststrahlen band overlapping said frequency band of use and presenting at least one interface with a dielectric medium, coupling means (330) allowing the resanant coupling of an interface phonon polariton (IPhP) supported by said interface and of an incident radiation (2) of pre-determined frequency lying in said frequency band of use and means of control (22) apt to modify the intensity of the coupling between said interface phonon polariton and said incident radiation (2) by modification of the dielectric function of the polar crystal in the Reststrahlen band of the polar crystal (10).

Abstract: A lighting emitting diode including: an n side layer and a p side layer formed by nitride semiconductors respectively; an active layer comprising a nitride semiconductor is between the n side layer and the p side layer; wherein, the n-side layer is successively laminated by an extrinsically-doped buffer layer and a compound multi-current spreading layer; the compound multi-current spreading layer is successively-laminated by a first current spreading layer, a second current spreading layer and a third current spreading layer; the first current spreading layer and the third current spreading layer are alternatively-laminated layers comprising a u-type nitride semiconductor layer and an n-type nitride semiconductor layer; the second current spreading layer is a distributed insulation layer formed on the n-type nitride semiconductor layer; and the first current spreading layer is adjacent to the extrinsically-doped buffer layer; and the third current spreading layer is adjacent to the active layer.

Abstract: A light emitting device package, comprises a light emitting structure having first and second electrodes insulated from each other; and a support structure. The support structure comprises: a first support electrode electrically connected to the first electrode of the light emitting structure; a second support electrode electrically connected to the second electrode of the light emitting structure, the second support electrode spaced apart from, and electrically insulated from, the first support electrode; and a support connection portion between the first support electrode and the second support electrode. The light emitting structure includes a protrusion portion that protrudes in a horizontal direction beyond a sidewall of at least one of the first support electrode and the second support electrode so that a void is present below the protrusion portion and above a plane extending from bottoms of the first and second support electrodes.

Abstract: The present disclosure is directed to LED components, methods and systems using such components, having light emitter devices with emissions tuned to meet CRI and LER goal values at a defined CCT. These emitter devices and methods may use a combination of light emitting diodes and quantum dots to tune the emission to meet these criteria. The quantum dots may incorporate additional features to protect the quantum dots from environmental conditions and improve heat dissipation, such as coatings and thermally conductive features.

Abstract: The present invention relates to a display device, comprising: a substrate comprising a display region and a non-display region surrounding the display region; a first conductive layer disposed on the substrate; a semiconductor layer disposed on the substrate and partially covering the first conductive layer; and a second conductive layer disposed on a top surface of the semiconductor layer; and there is a spacing between a first side of the semiconductor layer and a second side of the second conductive layer from a top view, wherein the first side of the semiconductor layer is adjacent to the second side of the second conductive layer; wherein the spacing in the display region is a first distance, the spacing in the non-display region is a second distance, and the first distance is smaller than the second distance.

Abstract: A semiconductor device includes a semiconductor body including a plurality of compound semiconductor layers and a two-dimensional charge carrier gas channel region formed in one of the compound semiconductor layers. The semiconductor device further includes a contact structure disposed in the semiconductor body. The contact structure includes a metal region and a doped region. The metal region extends into the semiconductor body from a first side of the semiconductor body to at least the compound semiconductor layer which includes the channel region. The doped region is formed in the semiconductor body between the metal region and the channel region so that the channel region is electrically connected to the metal region through the doped region.

Abstract: Embodiments of the present invention provide increased distance between vias and neighboring metal lines in a back end of line (BEOL) structure. A copper alloy seed layer is deposited in trenches that are formed in a dielectric layer. The trenches are then filled with copper. An anneal is then performed to create a self-forming barrier using a seed layer constituent, such as manganese, as the manganese is drawn to the dielectric layer during the anneal. The self-forming barrier is disposed on a shoulder region of the dielectric layer, increasing the effective distance between the via and its neighboring metal lines.

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.

Abstract: In accordance with an alternative embodiment of the present invention, a method for forming a semiconductor device includes applying a paste over a semiconductor substrate, and forming a ceramic carrier by solidifying the paste. The semiconductor substrate is thinned using the ceramic carrier as a carrier.

Abstract: A transistor device and a method for forming a fin-shaped field effect transistor (FinFET) device, with the channel portion of the fins on buried silicon oxide, while the source and drain portions of the fins on silicon. An example method includes receiving a wafer with a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. The method further comprises implanting a well in the silicon substrate and forming vertical sources and drains over the well between dummy gates. The vertical sources and drains extend through the BOX layer, fins, and a portion of the dummy gates.

Abstract: A device includes a pillar-shaped insulating layer above a first pillar-shaped semiconductor layer. A resistance-changing film is around an upper portion of the pillar-shaped insulating layer and a lower electrode is around a lower portion of the pillar-shaped insulating layer and connected to the resistance-changing film. A reset gate insulating film surrounds the resistance-changing film, and a reset gate surrounds the reset gate insulating film.

Abstract: A package structure includes an interposer, a die over and bonded to the interposer, and a Printed Circuit Board (PCB) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate. The interconnect structure and the redistribution lines are electrically coupled through the through-vias.

Abstract: In various embodiments, light-emitting devices incorporate smooth contact layers and polarization doping (i.e., underlying layers substantially free of dopant impurities) and exhibit high photon extraction efficiencies.