Abstract: A method for manufacturing a semiconductor device includes forming an SGT in a semiconductor pillar on a semiconductor substrate and forming a wiring semiconductor layer so as to contact a side surface of an impurity region present in a center portion of the semiconductor pillar or a side surface of a gate conductor layer. A first alloy layer formed in a side surface of the wiring semiconductor layer is directly connected to the impurity region and the gate conductor layer and is connected to an output wiring metal layer through a contact hole formed on an upper surface of a second alloy layer formed in an upper surface and the side surface of the wiring semiconductor layer.

Abstract: An optoelectronic device comprising a mesa structure including: a first and a second semiconductor portions forming a p-n junction, a first electrode electrically connected to the first portion which is arranged between the second portion and the first electrode, the device further comprising: a second electrode electrically connected to the second portion, an element able to ionize dopants of the first and/or second semiconductor portion through generating an electric field in the first and/or second semiconductor portion and overlaying at least one part of the side flanks of at least one part of the first and/or second semiconductor portion and of at least one part of a space charge zone formed by the first and second semiconductor portions, upper faces of the first electrode and of the second electrode form a substantially planar continuous surface.

Abstract: Provided are single photon devices, single photon emitting and transferring apparatuses, and methods of manufacturing and operating the single photon devices. The single photon device includes a carrier transport layer disposed on a conductive substrate and at least one quantum dot disposed on the carrier transport layer. A single photon emitting and transferring apparatus includes a single photon device, an element that injects a single charge into the single photon device described above, a light collecting unit that collects light emitted from the single photon device, and a light transfer system that transmits light collected by the light collecting unit to the outside.

Abstract: A manufacturing of a package carrier includes the following steps. Two base metal layers are bonded together. Two supporting layers are laminated onto the base metal layers respectively. Two release metal films are disposed on the supporting layers respectively. Each release metal film includes a first metal film and a second metal film separable from each other. Two first patterned metal layers are formed on the release metal films respectively. Each first patterned metal layer includes a pad pattern. Two dielectric layers are formed on the release metal films respectively and cover the corresponding first patterned metal layers. Each dielectric layer has a conductive via connecting to the corresponding pad pattern. Two second patterned metal layers are formed on the dielectric layers respectively. Each second patterned metal layer at least covers the conductive via. The base metal layers are separated from each other to form two independent package carriers.

Abstract: A semiconductor device may include interlayer insulating layers stacked in a first direction and separated from each other, word lines formed between the interlayer insulating layers, and sacrificial insulating layers formed between the interlayer insulating layers so that the sacrificial insulating layers are arranged at layers where the word lines are formed. The semiconductor device may also include cell contact plugs each including a first pillar portion passing through at least one of the interlayer insulating layers and the sacrificial insulating layers in the first direction, and a first protruding portion protruding from a sidewall of the first pillar portion and contacting a sidewall of one of the word lines, wherein the cell contact plugs have different depths.

Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; a third semiconductor layer of the first conductivity type formed on the second semiconductor layer; an opening part formed by removing part of the first to third semiconductor layers; a gate insulating film formed so as to cover an inner wall of the opening part; a gate electrode formed inside the opening part via the gate insulating film; a source electrode formed on a surface of the third semiconductor layer; a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode.

Abstract: Integrated circuits with magnetic random access memory (MRAM) and dual encapsulation for double magnesium oxide tunnel barrier structures and methods for fabricating the same are disclosed herein. As an illustration, an integrated circuit includes a magnetic random access memory structure that includes a bottom electrode that has a bottom electrode width and has bottom electrode sidewalls and a fixed layer overlying the bottom electrode that has a fixed layer width that is substantially equal to the bottom electrode width and has fixed layer sidewalls. The MRAM structure of the integrated circuit further includes a free layer overlying a central area of the fixed layer. Still further, the MRAM structure of the integrated circuit includes a first encapsulation layer disposed along the free layer sidewalls and a second encapsulation layer disposed along the bottom electrode sidewalls and the fixed layer sidewalls.

Abstract: An interconnect device and a method of forming the interconnect device are provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. One or more dielectric films are formed along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits, while using some of the pads as hard masks. The first opening and the second opening are filled with a conductive material to form a conductive plug.

Abstract: Embodiments of the present disclosure include a semiconductor device, a package and methods of forming a semiconductor device and a package. An embodiment is a semiconductor device including a molding material over a first substrate with a first opening having a first width in the molding material. The semiconductor device further includes a second opening having a second width in the molding material with the second width being greater than the first width. A first connector is in the first opening and a second connector is in the second opening.

Abstract: A method of fabricating multiple conductor layers utilizing the same seed layer is described. In an embodiment a stud bump structure is described in which the seed layer is encapsulated by the passivation layer. By forming the stud bump prior to the passivation layer, the height of the stud bump extending from the top surface of the passivation layer can be controlled.

Abstract: An aspect of the invention is a method of manufacturing a solar cell module in which wiring members are electrically connected to front and back electrodes on front and back sides of a solar cell with resin adhesion films. The total area of the front electrode is smaller than that of the back electrode. The method includes: arranging the resin adhesion films on the front and back electrodes; arranging a first cushion sheet and a lower press member below the lower resin adhesion film and arranging a second cushion sheet being thicker than the first cushion sheet and an upper press member above the upper resin adhesion film; pressing the press members against each other thereby bonding the resin adhesion films to the solar cell; and releasing the pressure to the press members and moving the first and second cushion sheets away from the solar cell.

Abstract: Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device.

Abstract: A method of fabricating a semiconductor device is provided that includes providing a material stack that includes a silicon layer, a doped semiconductor layer, and an undoped silicon germanium layer. At least one fin structure is formed from the material stack by etching through the undoped silicon germanium layer, the doped semiconductor layer, and etching a portion of the silicon-containing layer. An isolation region is formed in contact with at least one end of the at least one fin structure. An anodization process removes the doped semiconductor layer of the at least one fin structure to provide a void. A dielectric layer is deposited to fill the void that is present between the silicon layer and the doped semiconductor layer. Source and drain regions are then formed on a channel portion of the at least one fin structure.

Abstract: A resistance switching device having a high resistance variation ratio, an excellent response characteristic, an excellent resistance memory characteristic (retention characteristics) and an excellent repeat resistance. The resistance switching device comprises an n-type oxide semiconductor and first and second electrodes which are disposed so as to interpose at least a part of the n-type oxide semiconductor therebetween wherein a Schottky junction which provides resistance variation/memory characteristics by the application of voltage having different polarities between the first and second electrodes is formed at an interface between the n-type oxide semiconductor and the first electrode; and the first electrode is positioned such that it is in contact with the n-type oxide semiconductor, and has a lower layer which is formed from Au oxide or a Pt oxide or Au or Pt containing oxygen having the thickness of 1-50 nm.

Abstract: The present invention provides a memory structure including a resistance-changing storage element, which enables a reset operation with a reset gate and in which cross-sectional areas of a resistance-changing film and a lower electrode in a current-flowing direction can be decreased.

Abstract: Provided is a semiconductor device in which a reverse leakage current is suppressed and the mobility of a two-dimensional electron gas is high. A semiconductor device includes: an epitaxial substrate in which a group of group-III nitride layers are laminated on a base substrate such that a (0001) crystal plane is substantially in parallel with a substrate surface; and a Schottky electrode. The epitaxial substrate includes: a channel layer made of a first group-III nitride having a composition of Inx1Aly1Gaz1N (x1+y1+z1=1, z1>0); a barrier layer made of a second group-III nitride having a composition of Inx2Aly2N (x2+y2=1, x2>0, y2>0); an intermediate layer made of GaN adjacent to the barrier layer; and a cap layer made of AlN and adjacent to the intermediate layer. A Schottky electrode is bonded to the cap layer.

Abstract: A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.

Abstract: The present invention provides a memory structure including a resistance-changing storage element, which enables a reset operation with a reset gate and in which cross-sectional areas of a resistance-changing film and a lower electrode in a current-flowing direction can be decreased.

Abstract: A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate in at least one active region, a plurality of semiconductor channels having at least one end portion of each of the plurality of semiconductor channels extending substantially perpendicular to the major surface of the substrate, at least one memory film located between each of the plurality of control gate electrodes and each respective semiconductor channel of the plurality of semiconductor channels, and at least one first slit trench extending substantially perpendicular to the major surface of the substrate. Each of the plurality of control gate electrodes has a nonlinear side wall adjacent to the at least one first slit trench in the at least one active region.

Abstract: A method of assembling semiconductor devices with semiconductor dies of alternative different configurations uses the same substrate panel. The dies of the selected configuration are placed in an array, mounted, and connected to internal electrical contact pads on a first face of the panel using main fiducial markings and an array of subsidiary fiducial markings corresponding universally to arrays of semiconductor dies of the different alternative configurations. The pitch of the subsidiary fiducial markings is equal to the spacing between adjacent rows of the internal electrical contact pads on the panel and is a sub-multiple of the pitch of the array of dies.