Abstract: To provide a semiconductor device less affected by noise without making a manufacturing process more complicated and increasing a chip area. The device has a semiconductor substrate having first and second surfaces, a first-conductivity-type drain region on the second surface side in the semiconductor substrate, a first-conductivity-type drift region on the first surface side of a substrate region, a second-conductivity-type base region on the first surface side of the drift region, a first-conductivity-type source region on the first surface of the semiconductor substrate sandwiching a base region between the source and drift regions, a gate electrode opposite to and insulated from the base region, a wiring on the first main surface electrically coupled to the source region, and a first conductive film on the first main surface, opposite to and insulated from the wiring, and electrically coupled to the substrate region.

Abstract: A semiconductor device can reduce the number of bonding wires. The semiconductor device includes two or more semiconductor elements each of which has electrodes on a first main surface and a second main surface, an electrode plate that has one surface which is bonded to electrodes on the first main surfaces of the semiconductor elements, with a first bonding material layer interposed therebetween, and extends over the electrodes on the first main surfaces of the two or more semiconductor elements, and a conductive plate that includes a first lead terminal and a semiconductor element bonding portion which is bonded to electrodes on the second main surfaces of the semiconductor elements. A second bonding material layer is interposed therebetween, and is connected to the electrodes on the second main surfaces of the two or more semiconductor elements.

Abstract: A semiconductor memory device includes a plurality of word lines stacked in a first direction; a semiconductor pillar extending through the plurality of word lines in the first direction; a source line electrically connected to the semiconductor pillar; and a transistor arranged in the first direction with the plurality of word lines. The transistor includes a gate electrode, source and drain regions positioned on both sides of the gate electrode respectively. The source line is positioned between the transistor and the plurality of word lines, and is electrically connected to one of the source and drain regions.

Abstract: A semiconductor memory device includes first wires extending in a first direction; second wires provided in a first interconnect layer including the first wires, the second wires extending in the first direction along extension lines of the first wires respectively; third wires provided in a second interconnect layer different from the first interconnect layer; and transistors on/off controlling electrical connections between the first wires and the second wires through the third wires. The first and second wires are arranged respectively in a second direction crossing the first direction. The transistors are disposed in M stages (M is integer not less than 2) in the first direction, the M stages each including a transistor array aligned in the second direction. The first second wires are periodically arranged with the minimum period including M times N first wires (N is integer not less than 2) and M times N second wires.

Abstract: The present invention provides a manufacture method of a LTPS array substrate. By utilizing one halftone mask, the N type heavy doping, the channel doping of the first polysilicon layer of the NMOS region and the P type heavy doping of the second polysilicon layer of the PMOS region, the three processes which previously require three masks are integrated into one mask process, and two exposure processes are eliminated, which significantly raises the exposure capacity, and meanwhile saves the manufacture cost of two masks to effectively reduce the manufacture cost of the LTPS array substrate, and the manufactured LTPS array substrate possesses great electrical property.

Abstract: A device and method for fabricating a photovoltaic device includes forming a double layer transparent conductive oxide on a transparent substrate. The double layer transparent conductive oxide includes forming a doped electrode layer on the substrate, and forming a buffer layer on the doped electrode layer. The buffer layer includes an undoped or p-type doped intrinsic form of a same material as the doped electrode layer. A light-absorbing semiconductor structure includes a p-type semiconductor layer on the buffer layer, an intrinsic layer and an n-type semiconductor layer.

Abstract: A method for forming a semiconductor device includes forming device regions in a semiconductor substrate having a first side and a second side. The device regions are formed adjacent the first side. The method further includes forming a seed layer over the first side of the semiconductor substrate, and forming a patterned resist layer over the seed layer. A contact pad is formed over the seed layer within the patterned resist layer. The method further includes removing the patterned resist layer after forming the contact pad to expose a portion of the seed layer underlying the patterned resist layer, and forming a protective layer over the exposed portion of the seed layer.

Abstract: A semiconductor device includes a source including a first doped semiconductor layer arranged on a substrate, a layer of metal arranged on the first doped semiconductor layer, and a second doped semiconductor layer arranged on the layer of metal; a channel extending from the second doped semiconductor layer to a drain including an epitaxial growth; a gate disposed on sidewalls of the channel between the second doped semiconductor layer and the drain; an interlayer dielectric (ILD) disposed on the second doped semiconductor layer and the gate; and a source contact extending from a surface of the ILD to abut the layer of metal of the source.

Abstract: A transistor, an integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the transistor includes a source electrode, at least one semiconductor channel, a gate electrode, a drain electrode, and a drain pad. The source electrode is disposed in a substrate. The semiconductor channel extends substantially perpendicular to the source electrode. The gate electrode surrounds the semiconductor channel. The drain electrode is disposed on top of the semiconductor channel. The drain pad is disposed on the drain electrode, wherein the drain pad comprises a single implanted silicide layer or a multiple conductive layers with the implanted silicide layer.

Abstract: A quantum dot including a fluorine-containing ligand attached to a surface thereof and having a coating comprising a fluoropolymer over at least a portion of the outer surface of the quantum dot. A method for preparing a quantum dot with a coating comprising a fluoropolymer over at least a portion of the outer surface of the quantum dot is also disclosed. The method comprises contacting a quantum dot having a fluorine-containing ligand attached to a surface thereof with a fluoropolymer to coat the fluoropolymer over at least a portion of the outer surface of the quantum dot. A device including the quantum dot taught herein is further disclosed. An emissive material including the quantum dot taught herein is further disclosed.

Abstract: Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.

Abstract: A switching device including a semiconductor substrate including a trench (gate electrode) extending in a mesh shape is provided, and the upper surface of the semiconductor substrate is covered by the interlayer insulating film. Within an element range a contact hole is provided in an interlayer insulating film above each cell region while within a surrounding range an entire upper surface of each cell region is covered by the interlayer insulating film. The first metal layer covers the interlayer insulating film, and has recesses above the contact holes. The insulating protective film covers an outer peripheral side portion of the first metal layer within the surrounding range. The second metal layer covers the first metal layer within an opening of the insulating protective film. Within the surrounding range, a second conductivity-type region extending to below lower ends of the trench and is electrically connected to the body region, is provided.

Abstract: A method of fabricating an SRAM semiconductor device includes forming first and second FinFETs on an upper surface of a bulk substrate. The first FinFET includes a first source/drain region containing first dopants, and the second FinFET includes a second source/drain region containing second dopants. The method further includes selectively controlling a temperature of the second FinFET with respect to a temperature of the first FinFET during an anneal process to activate the first and second dopants such that the second source/drain region is formed having a different electrical resistance with respect to the first source/drain region.

Abstract: A magnetoresistive element according to an embodiment includes: a first layer containing nitrogen; a reference layer opposed to the first layer, the reference layer having a magnetization perpendicular to a face thereof opposed to the first layer, the magnetization of the reference layer being fixed; a storage layer disposed between the first layer and the reference layer, the storage layer having a magnetization perpendicular to a face thereof opposed to the first layer, the magnetization of the storage layer being changeable, and the storage layer including a second layer containing boron, and a third layer disposed between the second layer and the reference layer and containing boron, a boron concentration of the third layer being lower than a boron concentration of the second layer; and an intermediate layer disposed between the third layer and the reference.

Abstract: Provided is an LED element that ensures horizontal current spreading within an active layer, improving light-emission efficiency, without causing problems due to lattice mismatch in an n-type semiconductor layer adjacent to the active layer. This LED element is obtained by inducing c-axis growth of nitride semiconductor layers on a support substrate, and comprises a first semiconductor layer constituted of an n-type nitride semiconductor, a current-diffusion layer, an active layer constituted of a nitride semiconductor, and a second semiconductor layer constituted of a p-type nitride semiconductor. The current-diffusion has a hetero-structure having a third semiconductor layer constituted of InxGa1-xN (0<x?0.05) and a fourth semiconductor layer constituted of n-Aly1Gay2Iny3N (0<y1<1, 0<y2<1, 0?y3?0.05, y1+y2+y3=1), the third semiconductor layer having a thickness of 10 nm or more and 25 nm or less.

Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers that are stacked over one another in alternating fashion. The plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ and is in direct electrical contact with a lower surface of the upper metal layer.

Abstract: The invention provides a non-volatile memory device and methods for fabricating the same. The non-volatile memory device includes a non-volatile memory cell including a first transistor and a second transistor disposed on a substrate. The first and second transistors commonly use a first source region. A first gate of the first transistor and a second gate of the second transistor are different portions of a word line. First and second resistive switching elements are coupled to a first drain region of the first transistor and a second drain region of the second transistor. A first source line is coupled to the source region. First and second bit lines are coupled to the first and second resistive switching elements. The first source line, the first and second bit lines belong to a metal layer and are parallel to each other.

Abstract: According to an embodiment, a non-volatile memory device includes a first interconnection, a second interconnection closest to the first interconnection in a first direction, rectifying portions arranged in the first direction between the first interconnection and the second interconnection, and a first resistance change portion arranged between adjacent ones of the rectifying portions in the first direction. Each of the rectifying portions includes a first metal oxide layer and a second metal oxide layer.

Abstract: A light emitting device of an embodiment includes first and second light transmissive support bodies, and a light emitting diode is disposed between the bases. The light emitting diode includes a first semiconductor layer provided on a first surface (area S1) of a substrate, a light emitting layer (area S2), and a second semiconductor layer. A first electrode in a pad shape is formed on the second semiconductor layer. The light emitting diode has a shape satisfying a relation of “1?S1/S2??(3.46/H)+2.73”, where H is a distance from the first surface of the substrate to a surface of the first electrode.

Abstract: The present invention provides a memory structure including a resistance-changing storage element, which enables a reset operation with a reset gate and in which cross-sectional areas of a resistance-changing film and a lower electrode in a current-flowing direction can be decreased.