Abstract: Methods, systems, and devices for codeword rotation for zone grouping of media codewords are described. A value of a first pointer may be configured to correspond to a first memory address within a region of memory and a value of a second pointer may be configured to correspond to a second memory address within the region of memory. The method may include monitoring access commands for performing access operations within the region of memory, where the plurality of access command may be associated with requested addresses within the region of memory. The method may include updating the value of the second pointer bases on a quantity of the commands that are monitored satisfying a threshold and executing the plurality of commands on locations within the region of memory. The locations may be based on the requested address, the value of the first pointer, and the value of the second pointer.

Abstract: Methods, systems, and devices for transferring memory system data to a host system are described. A system may be configured for transferring information between a memory system and a host system in response to transitions between various operating modes, such as operating modes associated with different operating power levels. For example, before entering a reduced power mode, the memory system may identify information stored in a volatile memory array and transmit the identified information to the host system. Such information transmitted to the host system may be returned to the memory system to support memory system operation after exiting the reduced power mode. In some examples, such information exchanged between the memory system and the host system may be associated with a processing capability of the memory system, and the described operations may be referred to as suspending memory system processing information to a host system.

Abstract: A method, computer program product, and computer system for identifying, by a computing device, content in a first bucket in a first cache. It may be determined that a first portion of the content in the first bucket is a duplicate, wherein a second portion of the content in the first bucket may be unique. The first portion of the content in the first bucket may be deduplicated from the first cache. The second portion of the content may be stored in a second bucket in a second cache.

Abstract: Disclosed are apparatuses, methods, and computer-readable media for providing flexible command pointers to microcodes in a memory device. In one embodiment, a method is disclosed comprising receiving a command to access a memory device; accessing a configuration parameter; identifying a program counter value based on the configuration parameter and the command; and loading and executing a microcode based on the program counter.

Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

Abstract: Methods, systems, and devices that support efficient upload of firmware from memory are described. Multiple copies of a set of firmware may be stored across multiple planes of a memory device, such as with one respective copy within each of a set of planes. The copies may be staggered or otherwise offset in terms of page locations within the respective planes such that like-addressed pages within different planes store different subsets of the set of firmware. A controller may concurrently retrieve different subsets of the set of firmware, each of the different subsets included in a different copy, by concurrently retrieving the subsets stored at like-addressed pages within different memory planes. Upon loading the firmware code, the controller execute the firmware code to perform one or more further operations.

Abstract: Various embodiments comprise systems, methods, architectures, mechanisms, apparatus, and improvements thereof for in-memory computing using charge-domain circuit operation to provide energy efficient, high speed, capacitor-based in-memory computing. Various embodiments contemplate controlling input signal presentation within in-memory computing structures/macros in accordance with predefined or dynamic switch selection criteria to reduce energy consumption associated with charging and/or discharging summing capacitors during reset and evaluation operating modes of multiplying bit-cells (M-BCs).

Abstract: Methods, systems, and devices for multi-stage memory device performance notification are described. A memory system may include a first set of memory cells of a first type associated with a first performance level and a second set of memory cells of a second type associated with a second performance level. The memory system may have an interface and a control circuit coupled with the first and second sets of memory cells. The control circuit may be configured to determine a first parameter associated with a transition between the first performance level and the second performance level. The control circuit may also be configured to store the first parameter in a first register based at least in part on determining the first parameter.

Abstract: A memory controller controls a memory device including memory blocks, and can equalize wear levels of cores for controlling memory devices. The memory controller includes: cores for controlling the zones; a reset information controller for generating reset count values representing a number of reset requests input with respect to the zones, in response to a reset request, and generating reset count sum values obtained by summing reset count values of zones controlled by each of the cores; and a wear level manager for controlling the cores such that a core that is different from a first core having a highest reset count sum value from among the cores controls some of zones controlled by the first core according to whether a difference value between the highest reset count sum value and a lowest reset count sum value from among the reset count sum values exceeds a threshold difference value.

Abstract: According to one embodiment, a controller of a memory system executes communication with a host in conformity with a standard of NVM express. When fetching a command from a first submission queue, the controlled of the memory system determine the number of commands to be fetched with the number of free slots among a plurality of slots included in a first completion queue as an upper limit. The controller fetches the determined number of commands from the first submission queue.

Abstract: An illustrative unified data storage method includes providing, by a data storage system, block containers that represent a linear address space of blocks; and using, by the data storage system, the block containers to store content for a plurality of different data storage services. In certain examples, the different data storage services include at least one of a file storage service, an object storage service, or a database service.

Abstract: A host command is received to configure a system to have a configuration designating a first interface standard at a first port for exposing a storage element and a second interface standard at a second port for exposing a persistent memory region (PMR). The storage element is implemented on a first memory device of the system and the PMR is implemented on a second memory device of the system. The second interface standard implements one or more alternate protocols supported by the first interface standard. The system is configured in accordance with the configuration.

Abstract: A system and method for scheduling commands for processing by a storage device. A command is received from an application and stored in a first queue. Information is obtained on a first set of resources managed by the storage device. A second set of resources is synchronized based on the information on the first set of resources. The second set of resources is allocated into a first pool and a second pool. A condition of the second set of resources in the first pool is determined. One of the second set of resources in the first pool is allocated to the command based on a first determination of the condition, and one of the second set of resources in the second pool is allocated to the command based on a second determination of the condition.

Abstract: A method and system for retransmitting messages in a memory subsystem are described. A message is transmitted to a host system. A response message is expected to be received from the host system in response to the message. A determination that the response message was not received prior to detecting an indication of a processing of a number of commands from the host system is performed. The message is retransmitted to the host system in response to the determination.

Abstract: Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). A data storage device includes a main non-volatile memory (NVM) and a command queue that lists pending data transfer commands to transfer data between the NVM and a local memory. A collision manager predicts future collisions among the pending data transfer commands, such as but not limited to commands involving pending host commands from a host. A storage manager enacts a change in a storage policy to reduce a future rate of the predicted future collisions. The change in storage policy may involve duplication of write data so that the write data are written to multiple locations within the NVM. The change in storage policy may further involve a pre-emptive garbage collection operation upon an existing location to distribute current version data blocks to multiple locations within the NVM.

Abstract: A storage device having enhanced operating efficiency includes a memory device with a plurality of memory blocks and a memory controller that performs an operation of de-randomizing data stored in different memory blocks using an identical random seed. The memory controller includes a random table that has a first address group including physical page addresses of a first memory block and a second address group including physical page addresses of a second memory block. The random table also has a random seed group that includes random seeds corresponding to the first address group and the second address group.

Abstract: The present invention provides a microcontroller, wherein the microcontroller includes a processor, a first memory and a cache controller. The first memory includes at least a working space. The cache controller is coupled to the first memory, and is arranged for managing the working space of the first memory, and dynamically loading at least one object from a second memory to the working space of the first memory in an object-oriented manner.

Abstract: A method for managing overprovisioning in a solid state storage drive (SSD) array comprising (i) receiving usage data from each of a plurality of SSDs, (ii) determining a predicted service life value for each of the plurality of SSDs based on at least the usage data, (iii) comparing each of the predicted service life values with a predetermined service life value for each respective SSD, (iv) remapping at least one namespace in at least one of the plurality of SSDs among the plurality of SSDs, or reducing an available logical storage capacity for at least one of the plurality of SSDs. Here the remapping or reducing is based on a result of the comparing that the predicted service life value for the at least one of the plurality of SSDs is not greater than the predetermined service life value for that SSD.

Abstract: A method of queue design for data storage and management applies RAM data synchronization technology on many distributed nodes, both ensures storage performance and solves the problem of data loss in the system operation process; performs business separation and parallelize actions to optimize processing performance; uses simply extracted information instead of accessing the original information helps to speed up the processing ability and promptly detect events that exceed the threshold; allocates a fixed memory for the queue to ensure the safety of the whole system; in addition, provides monitoring and early warning of possible incidents. The method includes: step 1: build a deployment model; step 2: initialize the values when the application first launches; step 3: process write data to the queue; step 4: detect the threshold and process the data in the queue; step 5: remove processed data from the queue; step 6: monitor queue and early warn.

Abstract: Methods, devices, and systems for GPU cache injection. A GPU compute node includes a network interface controller (NIC) which includes NIC receiver circuitry which can receive data for processing on the GPU, NIC transmitter circuitry which can send the data to a main memory of the GPU compute node and which can send coherence information to a coherence directory of the GPU compute node based on the data. The GPU compute node also includes a GPU which includes GPU receiver circuitry which can receive the coherence information; GPU processing circuitry which can determine, based on the coherence information, whether the data satisfies a heuristic; and GPU loading circuitry which can load the data into a cache of the GPU from the main memory if on the data satisfies the heuristic.