Patents Examined by Cheryl R. Figlin
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Patent number: 5310966Abstract: A multi-layer wiring board where a plurality of wiring boards are laminated. The wiring board comprises a flexible insulating layer having a through hole and a wiring pattern formed on the flexible insulating layer. The wiring pattern is composed at least of two conductive layers. The first conductive layer formed on the insulating layer is made of a non-metallic conductor and the first wiring pattern is formed by a laser beam. The second conductive layer is an electroplated layer formed on the first wiring pattern. The first and second conductive layers have different reflectance for a beam.Type: GrantFiled: January 5, 1993Date of Patent: May 10, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Atsuko Iida, Hiroshi Odaira, Yoshizumi Sato, Yuichi Yamamoto
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Patent number: 5310965Abstract: To perform a stable wire bonding connecting against a multi-level wiring board using an organic material for the interlayer insulating film, a silicon oxide film and organic interlayer insulating films, for example, polyimide layers, and the first to the fourth level wirings, including a nickel layer by plating are formed on the surface of the silicon substrate as a base in order. By adjusting the thickness of the nickel layer in the wiring, the total Vickers hardness from the substrate to each wiring is adjusted to more than 100, respectively.Type: GrantFiled: August 28, 1992Date of Patent: May 10, 1994Assignee: NEC CorporationInventors: Naoji Senba, Atsushi Nishizawa
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Patent number: 5308928Abstract: A structure and method for selectively forming interconnections between the interconnect lines of a printed circuit board. At the same time solder is deposited through a solder application mask to bond the modules to the board, solder is also deposited on pad interconnect structures between the interconnect lines. Thus, line interconnections can be formed at minimal additional cost, reducing the number of different boards needed to mount different sets of modules or alternate component or circuit configurations. In a preferred embodiment, the pads comprise an arcuate member and an elongated member extending within the arc described by the arcuate member. By optimizing the spacing between the members, the total area of the members, and the volume of the solder, a highly reliable solder fillet interconnection can be formed.Type: GrantFiled: October 24, 1990Date of Patent: May 3, 1994Assignee: International Business Machines CorporationInventors: Anthony J. Parla, Howard F. Tepper
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Patent number: 5308927Abstract: A wiring board, which can be efficiency produced and has excellent heat resistance, and a method of manufacturing the same. With ion-irradiation, a conductive layer and a metal layer are formed in an insulating substrate. In the vicinity of the interface between the insulating substrate and the metal layer, a composition region, which includes the atoms of the insulating substrate and the metal layer, is formed by applying ions to a metal layer formed in the insulating substrate.Type: GrantFiled: June 18, 1993Date of Patent: May 3, 1994Assignee: Sumitomo Electric Industries, Ltd.Inventor: Norihiro Hosoi
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Patent number: 5308929Abstract: A via hole structure for interlayer connection formed in an insulating film and a process for the formation of the same. Via holes are formed in an insulating film of a multilayer interconnected board or the like so as to have a shape such that when a metallic film for wiring is formed on the insulating film, the metal film can completely fill up the via holes. The via holes are formed by gradually increasing from the bottom toward the top of an insulating layer 8 the apertures of the via holes 7 formed in the insulating layer 8, comprised of a plurality of insulating resin film or photosensitive insulating resin film layers 2, 5, in a multilayer interconnected board comprising the insulating layer 8 laminated alternately with a wiring layer 13 comprised of an electric conductor.Type: GrantFiled: July 27, 1992Date of Patent: May 3, 1994Assignee: Fujitsu LimitedInventors: Motoaki Tani, Shoichi Miyahara, Makoto Sasaki, Eiji Horikoshi, Isao Kawamura
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Patent number: 5306874Abstract: In order to form a (flexible) electrical interconnect structure a flexible dielectric substrate having a plurality of windows is laminated between a first, relatively thin flexible conductor layer and a second, relatively thick conductor layer. The first flexible conductor layer is patterned into a plurality of flexible conductor lines The second conductor layer is patterned into first and second pluralities of spaced apart terminals, which overlie the windows. Conductive vias are formed through the flexible dielectric substrate between the terminals and the flexible conductor lines, thereby connecting the terminals on one side of the flexible substrate to the flexible conductor lines on the other side of the substrate .Type: GrantFiled: July 12, 1991Date of Patent: April 26, 1994Assignee: W.I.T. Inc.Inventor: Richard M. Biron
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Patent number: 5306873Abstract: A load cell utilizable in a weighing apparatus. The load cell is fabricated by forming a strain gauge pattern (4) of a copper-nickel alloy on a surface of a strain inducing element (1) by the use of a sputtering technique and subsequently heat-treating the strain gauge pattern under an oxygen-free atmosphere, wherein the weight ratio of copper and nickel is chosen to be of a value effective to permit the temperature dependent coefficient of resistance of the strain gauge pattern (4), which undergoes shrinkage and expansion together with the strain inducing element (1), to be substantially zero. In this way, the load cell can be obtained which is not affected by a change in temperature and which gives a high measurement precision.Type: GrantFiled: May 27, 1992Date of Patent: April 26, 1994Assignee: Ishida Scales Mfg. Co., Ltd.Inventors: Takao Suzuki, Hiroyuki Konishi, Michito Utsunomiya
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Patent number: 5306872Abstract: The present invention relates generally to new decal structures, and more particularly to electrically conductive decals that are filled with organic insulator material. Various methods and processes that are used to make these electrically conductive decals filled with organic dielectric materials are disclosed.Type: GrantFiled: December 23, 1992Date of Patent: April 26, 1994Assignee: International Business Machines CorporationInventors: Mark R. Kordus, Mark S. Schneider, Louis H. Wirtz
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Patent number: 5304743Abstract: An improved multilayer integrated circuit package. The package, which has a plurality of layers of conducting leads, has metal vias which connects leads in a first layer connected to leads in a second layer. The improvement comprises having at least one of the vias with a cross-section such that the via is much larger in a first direction than in a second direction generally perpendicular to said first direction.Type: GrantFiled: May 12, 1992Date of Patent: April 19, 1994Assignee: LSI Logic CorporationInventors: Bidyut K. Sen, Eric S. Tosaya
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Patent number: 5300735Abstract: Described herein are interconnected mutilayer boards and their fabrication processes. Multilayer conductor lines of a skeleton structure are formed by conducting multilayer metallization while including all resist layers and metallic under-conductive layers and then removing the resist layers and metallic under-conductive layers at once. Spaces between the multilayer conductor lines of the skeleton structure are then filled with a solventless varnish so that insulating layers are formed. Modules making use of such interconnected multilayer boards and computers having such modules are also described.Type: GrantFiled: March 22, 1993Date of Patent: April 5, 1994Assignee: Hitachi, Ltd.Inventors: Hitoshi Yokono, Hideo Arima, Takashi Inoue, Naoya Kitamura, Haruhiko Matsuyama, Hitoshi Oka, Fumio Kataoka, Fusaji Shoji, Hideyasu Murooka, Masayuki Kyooi
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Patent number: 5298684Abstract: A circuit board with a lateral conductive pattern and shielded regions comprises a first contour cut laminate of a substrate having a conductive pattern of signal conductors and ground conductors on one side and a copper foil on the other side, covering the entire side. This laminate is laminated with the side provided with the conductive pattern to a second laminate also comprising a contour cut substrate and a copper foil provided on the substrate on the side opposite to the first laminate. Windows are cut in the substrate of the second laminate and are etched away in the top copper foil to enable mounting of components to the conductive pattern in the windows. A metal layer is provided to electrically connect said foil covering the entire other side of the first laminate with the ground conductors of the conductive pattern and the foil of the second laminate.Type: GrantFiled: June 12, 1992Date of Patent: March 29, 1994Assignee: Telefonaktiebolaget L M EricssonInventor: Karl-Erik Leeb
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Patent number: 5298685Abstract: Polymeric subcomposites of a circuit board are interconnected by metallic dendrites on electrical contact pads whereby electrical contact pads of one or the subcomposites are larger widthwise than electrical contact pads of the other subcomposite.Type: GrantFiled: July 14, 1992Date of Patent: March 29, 1994Assignee: International Business Machines CorporationInventors: Perminder S. Bindra, Ross Downey Havens, Voya R. Markovich, Jaynal A. Molla
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Patent number: 5298683Abstract: Connectors are provided which afford a substantial material match between two dissimilar metals, such as between an electronics package and the connector as well as between connector components to form an electronics assembly. In this manner, the thermal expansion properties of the electronics assembly components to be interfaced are also substantially matched, thereby allowing maintenance of a hermetic feedthru formed therebetween for a sustained period of operation. Additionally, the substantially matched component materials permit the use of simple and cost effective interfacing procedures in assembly construction.Type: GrantFiled: January 7, 1992Date of Patent: March 29, 1994Assignee: Pacific Coast TechnologiesInventor: Edward A. Taylor
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Patent number: 5298687Abstract: High density/heavy current hybrid circuit on a ceramic substrate, or other insulating board material, includes first screen printed silver, or copper, polymer seed layer for basic circuitry and bus bar around this circuitry outside the scribe lines, which is connected by removable silver filled polymer links with the circuitry and also the circuit elements are connected with each other by the same links in order to provide uniform electroplating. The links are protected before electroplating with a removable plating resist and they are removed after electroplating using an appropriate stripping solution. Then a permanent plating resist and dielectric polymer thick film isolation layer are applied (for crossovers) on which the second seed layer is applied, plating of the second metal layer occurs and so on until the desired number of layers are done.Type: GrantFiled: April 7, 1993Date of Patent: March 29, 1994Assignee: Remtec, Inc.Inventors: Nahum Rapoport, Michael Curley
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Patent number: 5298686Abstract: Both a system and method is provided for implementing a wiring change with respect to an electrical component detachably connected to a solderless PWB module. The system comprises at least one unused via on the PWB, an insulator used for electrically disconnecting a selected contact pad of the component from a contact pad disposed on the PWB, and a metallic strip mounted on a substrate for electrically connecting the selected component contact pad to the unused via. In one embodiment of the system, the substrate used to support the conductive strip is the compliant, insulative sheet material used in the interface that normally interconnects the pads of the electrical component with the pads of the PWB module. Alternatively, a separate "smart" layer formed from a thin insulative sheet material may be used to support the conductive strip.Type: GrantFiled: October 23, 1990Date of Patent: March 29, 1994Assignee: Westinghouse Electric Corp.Inventors: Robert A. Bourdelaise, David B. Harris, David R. King, Guy N. Hurst
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Patent number: 5296653Abstract: A multi-layered conductor structure device has a substrate, a first conductor layer formed on the substrate, which provides an electrode or wiring, and an insulating film covering the first conductor layer and the substrate. On the insulating film, a second conductor layer is formed which comprises an indium tin oxide, and which provides an electrode or wiring. The first conductor layer is formed of an alloy of aluminum with copper, gold, boron, bismuth, cobalt, chromium, germanium, iron, molybdenum, niobium, nickel, palladium, platinum, tantalum, titanium, tungsten, and/or silver.Type: GrantFiled: December 9, 1992Date of Patent: March 22, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Toshiya Kiyota, Mitsushi Ikeda, Meiko Ogawa, Yoshifumi Ogawa, Michio Murooka
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Patent number: 5296649Abstract: A plurality of pads are formed on a circuit board body at a pitch of 0.5 mm or less. The pads are formed such that a projecting height H of a pad from the board body surface and a width W of the pad satisfy a relation 2H<W, that a pad array is formed in which a width of each of the pads located at two ends of the pad array is larger than that of a pad located therebetween, and that the pad width W and a pad-to-pad distance D satisfy a relation W>D. A solder layer, obtained by a substitution reaction between a powder of a metal having the highest ionization tendency among metals constituting the solder layer or a powder of an alloy thereof and a salt formed by bonding the other metal or metals in the solder layer to an organic acid, is formed on each pad.Type: GrantFiled: March 17, 1992Date of Patent: March 22, 1994Assignees: The Furukawa Electric Co., Ltd., Harima Chemicals, Inc.Inventors: Izumi Kosuga, Kenichi Fuse, Takao Fukunaga, Hirokazu Shiroishi, Masanao Kohno, Hisao Irie
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Patent number: 5294755Abstract: A printed wiring board having a shielding layer for use in an integrated circuit is disclosed. The printed wiring board comprises an insulating sheet having a connecting through hole portion, a printed wiring circuit provided on one or both surfaces of the insulating sheet, an insulating layer having a thickness of 20.about.50 .mu.m which is provided on the printed wiring circuit, and an electromagnetic shielding layer provided on the insulating layer.Type: GrantFiled: October 4, 1991Date of Patent: March 15, 1994Assignee: Nippon CMK Corp.Inventors: Shin Kawakami, Satoshi Haruyama, Hirotaka Okonogi
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Patent number: 5293006Abstract: The base of solder bumps is preserved by converting the under-bump metallurgy between the solder bump and contact pad into an intermetallic of the solder and the solderable component of the under-bump metallurgy prior to etching the under-bump metallurgy. The intermetallic is resistant to etchants which are used to etch the under-bump metallurgy between the contact pads. Accordingly, minimal undercutting of the solder bumps is produced, and the base size is preserved. The solder may be plated on the under-bump metallurgy over the contact pad through a patterned solder dam layer having a solder accumulation region thereon. The solder dam is preferably a thin film layer which may be accurately aligned to the underlying contact pad to confine the wetting of the molten solder during reflow. Misalignment between the solder bump and contact pad is thereby reduced. The solder bumps so formed include an intermetallic layer which extends beyond the bump to form a lip around the base of the bump.Type: GrantFiled: August 7, 1992Date of Patent: March 8, 1994Assignee: MCNCInventor: Edward K. Yung
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Patent number: 5293501Abstract: A wiring harness is enshrouded in a tubular length of stretchable material. The shroud holds pigtails, takeouts, connectors, harness hold-downs and the like which otherwise extend from the harness against a trunk of the harness so that it can be inserted through an opening in a firewall or other structural member of a motor vehicle or other product for installation of the harness. Once inserted through the opening, the shroud is removed, preferably by means of a closure device which initially maintains the shroud as a tubular structure but can be removed to open at least a portion of the tubular structure to facilitate shroud removal. To facilitate installation of the shroud onto a wiring harness, the shroud is initially stretched over a tubular applicator to expand the shroud.Type: GrantFiled: September 6, 1991Date of Patent: March 8, 1994Assignee: Ford Motor CompanyInventors: Kelvin J. Bennett, Mark E. DeMott