Abstract: Poor sidewall coverage of vias in substrates for multi-chip modules is alleviated by forming pillars associated with conductors on an underlying metal wiring layer. In one embodiment, the pillars are disposed underneath the conductors, causing portions of the conductors to be pushed up through an overlying insulating layer towards a metal layer overlying the insulating layer. The pillars can be electrically conductive or insulating, and can be thermally conductive. In another embodiment, the pillars are disposed atop the conductors, thereby extending at least partially through the insulating layer. These pillars are electrically conductive.

Abstract: In a mounting board, two through-holes are formed which are used for inserting both ends of a supporting member for a vibrator. On a surface of the mounting board, a ground conductor pattern is formed. In the ground conductor pattern, two portions of arcs, where the ground conductor pattern is removed, are formed on respective peripheries of the two through-holes. Furthermore, on the mounting board, two connecting conductor patterns are formed on surfaces of portions defined by the two through-holes and so on, so as to extend from the ground conductor pattern. Both ends of the supporting member for the vibrator are respectively inserted into the two through-holes and soldered to two connecting conductor patterns.

Abstract: A method of preparing a Cu interconnection structure includes the following steps in the sequence: (a) depositing a Cu layer on a substrate layer; (b) depositing an Al layer on said Cu layer; (c) heating said Al layer and said Cu layer at a temperature ranging from 300.degree. C. to 550.degree. C. so as to transform said Al layer into a layer of alloy consisting of Al and Cu; and (d) depositing an insulating layer containing SiO.sub.2 on the alloy layer. Oxidation of Cu is suppressed by the formation of Al.sub.2 O.sub.3 on the outer surface of the alloy layer. Therefore, increase of electrical resistance of the Cu interconnection structure is substantially suppressed.

Abstract: A multilayer rigid-flex circuit board having two or more conductive layers, with at least one rigid circuit board electrically connected to at least one flexible jumper connector or intercircuit connector circuit board, is disclosed. A conductive layer of each of the rigid circuit boards is connected electrically and mechanically to a conductive layer of the flexible jumper connector by an interconnecting adhesive layer. The interconnecting adhesive layer comprises a conductive adhesive material having a plurality of deformable, electrically conductive particles dispersed substantially throughout a non-conductive adhesive. The fabricated multilayer circuit boards have interconnections which are reliable, heat resistant, and capable of withstanding the mechanical strain of the interconnection and the thermal cycling and typical circuit board fabrication, finishing and assembly processes. Such a rigid-flex circuit is typically used in an environment where space is limited.

Abstract: A connection for mounting an IC die directly to a substrate includes circuit runs deposited on the substrate with bond pad portions having metallization patterns forming ridges and cutout areas. Metal bumps made of gold or other highly conductive malleable material are placed atop the metallization patterns and are forced into the cutout areas between ridges as the dies are compressed onto the substrate. This locks the dies to the circuit run bond pads so as to resist thermal stress and high humidity.

Abstract: An optimal routing methodology for routing high I/O density packages which minimizes the number of PCB layers required. One feature of this routing methodology comprises treating respective I/O that are routed at the top layer of the package as surface mount technology (SMT) pads without dropping vias within the BGA grid, as is commonplace in the industry. This facilitates the use of fewer escapes and allows for more efficient use of the available space. Signal lines on the top layer of the package which must be routed to other layers of the PCB are connected to vias outside of the area of local high signal density on the printed circuit board. The placement of vias outside the area of local high density, i.e., in a depopulated area, reduces the number of layers necessary in the PCB to properly route the signals. This placement also facilitates the use of filtering capacitors to meet EMI requirements. In addition, all voltage pins are placed on the innermost or outermost grids and have clearanced vias.

Abstract: In a master slice integrated circuit, a number of connection pads are located in a peripheral edge region of a chip in such a manner that each one power supply pad is interposed between each pair of signal input/output pads and a number of unitary pad arrays each of which consists of a signal pad, a power supply pad and another signal pad located in the named order are repeatedly arranged along a peripheral edge of the chip. Thus, the pad pitch can be reduced to two thirds of the width of an I/O cell, without changing the I/O cell size. In addition, since the power supply pad is located adjacent each of the I/O cells, it is effective to suppress or minimize the power supply voltage noise caused by the simultaneous driving.

Abstract: An object of this invention is to provide a circuit board low in manufacturing cost in which aimed circuit patterns having a circuit gap therebetween can be short-circuited substantially irrespective of the length of the circuit gap while being insulated from other circuit patterns which are laid in the circuit gap. In a circuit board on which a plurality of circuit patterns are arranged, a selected one of circuit patterns is cut to have a circuit gap where the selected circuit pattern is laid across the remaining circuit patterns, in such a manner that the circuit gap divides the selected circuit patterns into two parts, a conductor formed by cutting a wire to the length of the circuit gap bridges the circuit gap, to short-circuit the two parts thereby to complete the selected circuit pattern, the conductor being insulated from the remaining circuit patterns laid across the circuit gap.

Abstract: A circuit control device includes two intermating foil pads separated from one another by a narrow gap having a maximum dimension of 0.006 inches. A circuit path having one side connected to one of the pads and a second side connected to the other of the pads is selectively closed and opened by solder application and removal operations. Interdigitated, triangular fingers which are intermated to form the device ensure the formation of acutely angled junctures along the gap to ensure solder bridging of the gap. Emergency control elements are coupled to the circuit control device to permit control of an associated circuit path if the circuit control device itself fails. In that event, an emergency control device is coupled to the emergency control elements to control opening and closing of the circuit path.

Abstract: A metal base (1), and holes (12) therein, of a printed circuit board are given an insulating coat (2) produced from an epoxy compound in particulate form which is deposited and machined successively at either side. An insulating topology (16) in a photoresist imposed on the insulating coat (2) is metal-plated in vacuum. On removing the metal from the prominent portions of the topology (16) tracks (4) and connecting pads (5) of a layer (3) of conducting pattern are left. An insulating topology (18) consistent with the disposition of connecting pads (11) and connecting posts (10) interconnecting the layers (3, 6) of conducting patterns is formed and metal-plated. On removing the metal from the prominent portions an insulating layer (9) with connecting posts (10) and connecting pads (11) is left. Next, an insulating topology (19) consistent with the topology of the layer (6) of conducting pattern is formed and metal-plated.

Abstract: A process for fabricating embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias or contacts. A conductive ground plane disposed between two dielectric layers has vias formed by removing insulating dielectric and conductive ground plane material according to a single photo-lithography masking operation. A sidewall insulator formed on vertical sidewalls of the vias, electrically isolates the ground plane from interconnect metal passing from a lower interconnect layer to an upper interconnect layer through the vias. Alternatively, shielding structures incorporating multiple sidewall insulators and upper and lower shielding may be fabricated to entirely encapsulate the lower interconnect metal from external environments. Process efficiency and yield are increased due to the simplified processing of the embedded ground plane and shielding structures.

Abstract: An improved multilayer integrated circuit package. The package, which has a plurality of layers of conducting leads, has metal vias which connects leads in a first layer connected to leads in a second layer. The improvement comprises having at least on of the vias with a cross-section such that the via is much larger in a first direction than in a second direction generally perpendicular to the first direction.

Abstract: Disclosed herein is a flexible wiring cable being provided on its forward end with a connecting portion to be connected with a connector, which comprises a base film, a wiring conductor provided on the base film, a dielectric member electrically connected with the wiring conductor in the connecting portion of the base film, and a ground electrode electrically connected with the dielectric member for forming a capacitor with the wiring conductor.

Abstract: A circuit board comprising a substrate, at least one dielectric film formed on the substrate and made of at least one selected from the group consisting of AlN, BN, diamond, diamond-like carbon, BeO and SiC, the dielectric film having pores of a porosity of 5 to 95% by volume, and at least one wiring metal film formed on the dielectric film.

Abstract: A thick film resistive network circuit board to be potted is given a surface coat of epoxy on one side which does not cover the solder pads or electrical connections, thereby allowing further working of the board. The epoxy coat is applied in such a fashion that it does not obscure or cover a second side of the board having a potentiometer network thereon in the preferred embodiment. The epoxy coat provides a good surface for adhesion of a potting epoxy as well as good adhesion to the board, and thereby prevents breakdown of the dielectric properties of the high voltage circuitry into which the board is fitted.

Abstract: A transmission line structure including a central signal conductor stack of elongated conductive strips separated from each other by contiguous dielectric layers of a unitized multilayer circuit structure, a first ground conductor stack of elongated conductive strips separated from each other by contiguous dielectric layers and laterally separated from one side of the central signal conductor stack, and a second ground conductor stack of elongated conductive strips separated from each other by contiguous dielectric layers and laterally separated from another side of the central signal conductor stack such that the central conductor stack is laterally between the first and second ground conductor stacks.

Abstract: A two-layer or multilayer printed circuit board (1) comprises a support plate (2) carrying a first conductor pattern (3) and a second conductor pattern (21) which is connected to the support plate (2) via an adhesive layer (13) consisting of adhesive material, a solder-stop layer (30) being applied to the second conductor pattern.

Abstract: A printed circuit board and a method for making same is disclosed whereby a very high wiring density is provided in those regions of the printed circuit board in which external components (e.g., semiconductor chips) are to be attached directly. An automated registration routine permits very precise registration and positioning in those regions.

Abstract: A ceramic substrate has a single plating film formed on both wiring electrodes formed on an upper surface of a ceramic body and external electrodes formed on side surfaces and a lower surface of the ceramic body. The plating film on the wiring electrodes and the external electrodes has a first plating layer made of Ni and a second plating layer made of Sn.

Abstract: An improved surface mount package and method of making such a package is provided. A conventional surface mount package is modified by fabricating a U-shaped via around the lead via to form a quasi-coaxial transmission line through the insulating substrate. This permits the electrical impedance in the conductive elements of the surface mount package to be controlled to reduce insertion loss and return loss, and to improve isolation. The surface mount package includes a lead frame, and a gold plate to which an integrated circuit in the package is attached. The package is sealed with a ring-frame and a lid. Ground vias connecting the lead-frame to the plate through the substrate may also be included. The present package is designed by modelling the various elements of the package as a coaxial transmission line, a co-planar waveguide, and a single lead in a trough transmission line in combination.