Abstract: A non-tacky, solid, adhesive composition comprising: (a) at least one film forming polymeric resin of number average molecular weight (Mn) of at least about 10,000 and having a hydroxyl, epoxide or unsaturated functionality greater than about 7, the polymeric resin being selected from the group of polyols consisting of polyesters, polyurethanes, phenoxies, epoxies and mixtures thereof; a plasticizer present in an amount which permits the activation without C-staging of the polymeric resin; (b) a curing agent which is capable of crosslinking and curing the polymeric resin to a C-stage, the curing agent being present in an amount sufficient to C-stage the polymeric resin. The adhesive composition can be activated without C-staging the polymeric resin, upon application of sufficient heat or ultrasonic energy for a time period less than one second.

Abstract: The present invention relates generally to new structures for decals, and more particularly to electrically conductive decals filled with inorganic insulator material. Various methods and processes that are used to make these electrically conductive decals filled with inorganic dielectric material are disclosed.

Abstract: The invention relates to a multilayer printed circuit board, in particular, for high-frequency operation, having least an outer, plane dielectric layer for accommodating interconnection paths of equal cross-section and component as well as further alternately provided metallic and dielectric layers for forming a reference earth and for the voltage supply to said interconnection paths and components via plated-through holes.

Abstract: An interconnect structure for connecting an integrated circuit (IC) chip to a supporting substrate is described. The supporting substrate serves to communicate signals between the IC chip and the "outside world," such as other IC chips. In one embodiment, the interconnect structure comprises an interconnect substrate having a first post disposed on one of its surfaces and a second post disposed on another of its surfaces. One post is for contacting the IC chip and the other is for contacting the major substrate. Each post comprises an elongated body having top and bottom ends, with the bottom end being mounted to one of the substrate surfaces and the top end having a substantially flat surface which is substantially co-planer with the substrate surface. The interconnect substrate further comprises a device for de-concentrating the mechanical stain present at one or both of the top and bottom ends of each post.

Abstract: A method for reducing defects in an integrated circuit conductive lines characterized by the steps of providing a conductive line and contacting the conductive line with a layer which reduces stress in the line. There are several mechanisms by which the layer can accomplish the desired stress reduction. One method provides a resilient passivation layer over the conductive line and another method provides a resilient layer beneath the line. Yet another method creates a thin, flexible oxide layer over the conductive line. An extension of this latter method provides a resilient buffer layer over the thin oxide layer and a thick oxide layer over the resilient layer. Another form of stress-reducing layer includes an anti-diffusion layer which reduces the diffusion of metal atoms of the conductive layer into the surrounding oxide. A conductive line structure of the present invention includes at least one conductive line and at least one layer contacting the conductive line which reduces stress in the line.

Abstract: A method is provided for forming a substantially planarized surface of an integrated circuit, and an integrated circuit formed according to the same. A conductive area is formed over a portion of a dielectric region. A first spin-on-glass layer is formed over the conductive area and exposed dielectric region. A second spin-on-glass layer is formed over the first spin-on-glass layer; wherein the second spin-on-glass layer has a slower etch rate than the first spin-on-glass layer. A partial etchback of the first and second spin-on-glass layers is performed forming a substantially planar surface.

Abstract: A structure and method for forming contact structures in integrated circuits. A buffer layer is formed over an underlying conductive element. A first conductive layer is then deposited over the buffer layer and patterned to define a first interconnect layer. While the first interconnect layer is patterned, the buffer layer protects the underlying conductive element from damage. Portions of the buffer layer which are not covered by the first interconnect layer are then removed, and a second conductive layer is deposited over the integrated circuit. The second conductive layer is then anisotropically etched to form conductive sidewall spacers alongside the vertical sidewalls of the first interconnect layer, where at least one of the conductive sidewall spacers makes electrical contact with the underlying conductive element. Therefore, a conductive contact is made between the underlying conductive element and the first interconnect layer through at least one of the conductive sidewall spacers.

Abstract: A mounting device for mounting an electronic device on a substrate is described. The electronic device has a plurality of interconnection pins for engagement with corresponding through-holes on the substrate for electric interconnection. The mounting device incorporates a plate member of an insulating material provided with a plurality of counter-bores on an upper major surface of the plate member in correspondence to the interconnection pins of the electronic device, a plurality of through-holes provided on the plate member in correspondence to each of the counter-bores in a concentric relationship to the counter-bore, and a plurality of solder rings provided on the plurality solder rings provided on the plurality of counter-bores.

Abstract: Disclosed is a method of fabricating an electronic interconnection structure comprising at least one solder column Joined to an I/O pad of a substrate, the method including the steps of:(a) applying a quantity of solder to the solder column or I/O pad;(b) aligning the solder column with the I/O pad such that there is a quantity of solder between them;(c) heating the structure to cause the solder to melt and bond the column to the I/O pad; and(d) planarizing the solder column to a predetermined height.Also disclosed is the electronic interconnection structure made by the method according to the invention.

Abstract: Polyetherimide-metal laminates are formed by etching the surfaces of a polyetherimide web with a glycol-containing etchant followed by electroless nickel or cobalt deposition and then by copper deposition. The glycol-containing etchant can be utilized to form through holes through the web.

Abstract: The invention is an interleaved electrical cable and a method of manufacture therefor. The cable is manufactured by interleaving the electrical traces of two cable subassemblies. Two cable subassemblies are manufactured and then bonded together with the traces of each subassembly interleaved with each other. The resulting interleaved fine line cable includes traces of a pitch less than that of either subassembly. Interleaved flexible cable subassemblies are also used to create the aforementioned traces of reduced pitch with one or more simple trace crossovers.

Abstract: An easily peelable or chemically strippable laminate and method of making same comprising an aluminum carrier, an aluminum oxide layer, which is at least 800 Angstroms thick and deposited on the aluminum carrier, copper foil electrodeposited on the aluminum oxide layer and optionally, a brass layer electrodeposited on the copper foil have been discovered. Such laminates find utility in the electronics industry in the fabrication of printed circuit boards and afford an ease of strippability of the protective aluminum carrier-aluminum oxide layer heretofore unknown in the industry. The protective aluminum carrier-aluminum oxide layer of the laminates of the present invention may also be chemically etched away providing a universal carrier for copper foil.

Abstract: A polyimide multilayer wiring board is constructed by using a plurality of laminated blocks each of which has a plurality of wiring layers and interlaminar insulating layers of polyimide. On a base block having a substrate, the other blocks are laid on top of another, bonded to each other with a polyimide used in each block or another adhesive and electrically connected to each other by using, for example, metal bumps formed on each block. Each of the blocks except the base block is formed on a temporary substrate, and the temporary substrate is removed after bonding each block to the base block or precedingly bonded blocks. This multilayer wiring board can be produced in a shortened time with increased yield.

Abstract: A structure and method for forming contact vias in integrated circuits. An interconnect layer is formed on an underlying layer in an integrated circuit. A buffer region is then formed adjacent to the interconnect layer, followed by forming an insulating layer over the integrated circuit. Preferably, the insulating layer is made of a material which is selectively etchable over the material in the buffer region. A contact via is then formed through the insulating layer to expose a portion of the interconnect layer. During formation of the contact via, the buffer region acts as an etch stop and protects the underlying layer. The buffer region also ensures a reliable contact will be made in the event of an error in contact via placement.

Abstract: A coil integrated semi-conductor device and method of making the same is disclosed. First to third metal layers are in sequence formed on a semi-conductor device. The first and third metal layers of equal width are connected to each other through contact holes, to define a hollow region which is filled with the second metal layer disposed centrally therein and a circumferential region surrounding the second metal layer. The first and third metal layers are used as a coil and the second metal layer is used as a core of magnetic material. The circumferential region surrounding the second metal layer is filled with different dielectric layers. According to the invention, a coil capable of exerting the magnetic field effect can be integrated in a semiconductor chip. This makes it possible contemplation of compactness, integration and preciseness of devices in the form that the coil is wound around the care.

Abstract: A double-sided printed wiring board includes a base plate having a copper foil laminated on each of the opposite sides thereof. The copper foil-laminated base plate has through-holes extending therethrough, and at least one of the through-holes is internally plated for providing a through-via-hole into which a resin filler is provided and solidified. A closed through-via-hole is thus obtained. The copper foil-laminated base plate including the closed through-via-hole is copper-plated, and a particular wiring pattern is formed thereon. A chip land is formed in alignment with the closed through-via-hole.

Abstract: The present invention relates to a printed wiring board and a method of manufacturing a printed wiring board. A first printed wiring board and a second printed wiring board, each including an insulating layer and a copper foil layer, are superposed on one another with a middle insulating layer therebetween with blind holes formed in the insulating layers of the boards to oppose one another, through-holes are formed and provided with conductive plating to electrically connect the copper foil layers with each other, and reflow pads are formed by etching in the copper foil layers to seal the blind holes. The blind holes are formed through the insulating layers and reach the copper foil layers. Plated layers are plated on the surfaces of the printed wiring boards on the sides thereof where the blind holes are formed to electrically connect the blind holes and the copper foil layers, respectively.

Abstract: An EMR reduction technique using grounded conductive traces and vias circumscribing the internal planes of printed wiring boards. Conductive vias are placed in a circuitous path near the border and encircling the signal traces of each layer of a printed circuit board. The ground plane is extended to encompass and electrically ground each of the vias. For each signal plane, a conductive trace is routed and connected to each of the vias forming a grounded shield around the signal-carrying traces on the signal plane. For the power planes, a conductive trace is also provided connecting the conductive vias and forming a grounded shield around the power planes. A non-conductive path is provided between the power plane and the power plane conductive trace to electrically isolate the voltages of the power plane from the grounded conductive trace.

Abstract: A method for applying solder to printed wiring boards includes producing a printed wiring board with electrically conductive regions. Soldering paste is applied as a solder deposit on the electrically conductive regions. The solder deposits are melted to form hump-shaped solid solder applications joined to the printed wiring board. The hump-shaped solder applications are levelled out by areally applying pressure to the solder applications in the direction of the printed wiring board. A printed wiring board to which solder has been applied includes a wiring board surface having regions to be equipped with components according to an SMD process. Solder applications are disposed on the regions in the form of a solid solder layer. The solid solder layer has a pressed or rolled surface extended substantially parallel to the wiring board surface.

Abstract: A conductive line is applied to a substrate by aligning the conductive line in juxtaposition with a selected area of the substrate; bonding the conductive line to the substrate; and detaching the conductive line from a carrier in which the conductive line is suspended. The carrier has a carrier opening defined by sidewalls, and conductive material is suspended by the sidewalls of the carrier opening so as to be embedded within the carrier opening, and form the conductive line.