Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.
Abstract: Aspects of the present invention relate to the arrangement of points of interconnection of integrated circuit die to the package in which they are enclosed. More specifically, aspects of the present invention pertain to an arrangement of bond pads over the active circuitry of an integrated circuit die, in order to permit a reduction in size of the die. An embodiment of the present invention may place a first bond pad over the active area of an integrated circuit, wherein the first bond pad is electrically coupled to a second bond pad outside of the active area of the integrated circuit. Production and delivery of the integrated circuit may proceed using the second bond pad during packaging, in parallel with the testing of packaging using the first bond pad. When processes related to the use of the first bond pad have been proven successful and sustainable, the second bond pad may be eliminated, resulting in a reduction of the size of the integrated circuit device.
Abstract: The semiconductor device concerning the present invention has a wiring substrate, a semiconductor chip, under-filling resin, a reinforcement ring, a heat spreader, a power supply pattern and a wiring layer under surface via land which are formed on the wiring substrate and spaced out by a clearance region, an insulating film, a wiring layer via land, a via, and a wiring which is formed on the insulating film, passes over the clearance region, and connects the wiring layer via land to the semiconductor chip. The wiring layer via land is formed between the semiconductor chip and the reinforcement ring, and within a region of a 1 mm width from the extension line of the diagonal line of the semiconductor chip. The angle of the lead-out direction of the wiring from a wiring layer via land to the extension line of the diagonal line of the semiconductor chip is 20° or more.
Abstract: Composite interconnect structure forming methods using injection molded solder are disclosed. The methods provide a mold having at least one opening formed therein with each opening including a member of a material dissimilar to a solder to be used to fill the opening, and then fill the remainder of each opening with solder to form the composite interconnect structure. The resulting composite interconnect structure can be leveraged to achieve a much larger variety of composite structures than exhibited by the prior art. For example, the material may be chosen to be more electrically conductive than the solder portion, more electromigration-resistant than the solder portion and/or more fatigue-resistant than the solder portion. In one embodiment, the composite interconnect structure can include an optical structure, or plastic or ceramic material.
January 31, 2006
Date of Patent:
August 31, 2010
International Business Machines Corporation
David D. Danovitch, Mukta G. Farooq, Michael A. Gaynes
Abstract: A processor/cache assembly has a processor die coupled to a cache die. The processor die has a plurality of processor units arranged in an array. There is a plurality of processor sets of contact pads on the processor units, one processor set for each processor unit. Similarly, the cache die has a plurality of cache units arranged in an array. There is a plurality of cache sets of contact pads on the cache die, one cache set for each cache unit. Each cache set is in contact with one corresponding processor set.
Abstract: An integrated circuit for driving a semiconductor device, which is adaptable for demands, such as a higher output (larger current), a higher voltage, and a smaller loss, and has a small size, is produced at a low cost, and has high reliability. A power converter including such an integrated circuit is also provided. Circuit elements constituting a drive section of an upper arm drive circuit 212, a level shift circuit 20 including a current sensing circuit 210, a drive section of a lower arm drive circuit 222, and a drive signal processing circuit 224 are integrated and built in one high withstand voltage IC chip 200. Circuit elements constituting a final output stage buffer section 213 of the upper arm drive circuit 212 are built in a vertical p-channel MOS-FET chip 213p and a vertical n-channel MOS-FET chip 213n.
Abstract: An economical miniaturized assembly and connection technology for LEDs and other optoelectronic modules is provided. A manufactured item in accordance with this technology includes a substrate with an optoelectronic component contacted in a planar manner.
October 27, 2004
Date of Patent:
July 20, 2010
OSRAM Opto Semiconductors GmbH
Ewald Gunther, Jorg-Erich Sorg, Karl Weidner, Jorg Zapf
Abstract: There are included a semiconductor substrate provided with a desirable element region, an electrode pad formed to come in contact with a surface of the semiconductor substrate or a wiring layer provided on the surface of the semiconductor substrate, a bonding pad formed on a surface of the electrode pad through an intermediate layer, and a resin insulating film for covering a peripheral edge of the bonding pad such that an interface of the bonding pad and the intermediate layer is not exposed to a side wall.
Abstract: A first wiring layer in a circuit substrate structure is provided with a first inductor and a second inductor. A dielectric layer is provided with a first via and a second via electrically connected to the first inductor and the second inductor, respectively. A second wiring layer is provided with: a bridge electrically connecting the first via and the second via; and a conductive pattern provided around the bridge, the outer edge of the conductive pattern being located outside the outer edge of the first wiring pattern and the second wiring pattern in the first wiring layer. The bridge functions as a coplanar line and suppresses generation of electromagnetic field.
Abstract: A member for a semiconductor device of low price, capable of forming a high quality plating layer on a surface, having heat conductivity at high temperature (100° C.) of more than or equal to 180 W/m·K and toughness that will not cause breaking due to screwing, and will not cause solder breaking due to heat stress when it is bonded to other member with solder, and a production method thereof are provided. A member for a semiconductor device (1) having a coefficient of thermal expansion ranging from 6.5×10?6/K to 15×10?6/K inclusive, and heat conductivity at 100° C.
Abstract: An integrated circuit packaging system comprised by providing a substrate with a first surface including conductive regions for receiving a flip chip die and a second surface including electrical contacts for external electrical connections. Providing the flip chip die over the substrate. Depositing a controlled volume of resin between the first surface of the substrate and the flip chip die and adhering the flip chip die to the first surface of the substrate to form the controlled volume of resin into a zero fillet resin.
Abstract: A heat dissipating package structure includes a chip carrier; a semiconductor chip mounted and electrically connected to the chip carrier; a heat spreader having a first surface, an opposed second surface and a hollow structure, the second surface of the heat spreader being mounted on the chip, wherein the chip is larger in size than the hollow structure such that the chip is partly exposed to the hollow structure; an encapsulant formed between the heat spreader and the chip carrier, for encapsulating the chip, wherein the first surface and sides of the heat spreader are exposed from the encapsulant to dissipate heat produced from the chip; and a plurality of conductive elements disposed on the chip carrier, for electrically connecting the chip to an external device. The present invention also provides a method for fabricating the heat dissipating package structure.
Abstract: A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package.
May 3, 2007
Date of Patent:
June 29, 2010
Belgacem Haba, Masud Beroz, Teck-Gyu Kang, Yoichi Kubota, Sridhar Krishnan, John B. Riley, III, Ilyas Mohammed
Abstract: An avalanche photodetector is disclosed. An apparatus according to aspects of the present invention includes a semiconductor substrate layer including a first type of semiconductor material. The apparatus also includes a multiplication layer including the first type of semiconductor material disposed proximate to the semiconductor substrate layer. The apparatus also includes an absorption layer having a second type of semiconductor material disposed proximate to the multiplication layer such that the multiplication layer is disposed between the absorption layer and the semiconductor substrate layer. The absorption layer is optically coupled to receive and absorb an optical beam. The apparatus also includes an n+ doped region of the first type of semiconductor material defined at a surface of the multiplication layer opposite the absorption layer.
Abstract: A semiconductor die package including at least two heat sinks. The semiconductor die package includes a first heat sink, a second heat sink coupled to the first heat sink, and a semiconductor die between the first heat sink and the second heat sink. The semiconductor die is electrically coupled to the first heat sink and the second heat sink. The semiconductor die may also be attached to a lead.
Abstract: An integrated circuit package system including a plurality of substrates and a plurality of semiconductor devices formed on each of the substrates. An edge connection system is provided and an electrical edge connector on each of the substrates is for attachment to the edge connection system. A vertically stacked configuration of the substrates is formed by attaching the substrates to the edge connection system.
May 30, 2006
Date of Patent:
June 8, 2010
STATS ChipPAC Ltd.
Byung Joon Han, Il Kwon Shim, Seng Guan Chow
Abstract: A difference in delay of signal transmission due to the wiring within a board is minimized. A wiring board includes wiring for connecting terminals included in one of a plurality of semiconductor chips to terminals included in another one of the plurality of semiconductor chips, through branch points. Each of the plurality of semiconductor chips includes first and second terminals. Moreover, a first wiring up to the first terminals and a second wiring up to the second terminals are in a positional relationship of being shifted parallel to each other in a planar direction of the wiring board so as not to come into electrical contact with each other.
Abstract: A method for manufacturing a semiconductor chip having through electrodes includes forming, in a semiconductor wafer, a plurality of electrode forming holes for forming through electrodes, superimposing bump forming masks formed with a plurality of bump holes over the front and back surfaces of the semiconductor wafer respectively so that the electrode forming holes and the bump holes are brought into alignment, placing the semiconductor wafer with the bump forming masks superimposed thereon over a stage, embedding conductive paste into the bump holes and the electrode forming holes from the bump forming mask disposed over the surface on the side opposite to the stage, of the semiconductor wafer, detaching the bump forming masks from the semiconductor wafer after the conductive paste has been embedded, and dividing the semiconductor wafer into fractions after the bump forming masks have been detached.
Abstract: A fan-out wire structure is used to connect a driver and a display region of a display panel and has a plurality of first single-layer wires and at least one second single-layer wire. The first ends of the first single-layer wires are connected to the driver, and the second ends of the first single-layer wires are connected to the display area. The first end of the second single-layer wire is connected to the driver, and the second end of the second single-layer wire is connected to the display area. A metal layer of the first single-layer wires is different from a metal layer of the second single-layer wire.
Abstract: A package substrate for a multi-package module. The package substrate comprises a substrate having a die region and at least one thermal channel region outwardly extending to an edge of the substrate from the die region. An array of bumps is arranged on the substrate except in the die and thermal channel regions, in which the interval between the bumps is narrower than the width of the thermal channel region. An electronic device with a package substrate is also disclosed.