Abstract: A semiconductor device including: a semiconductor substrate in which an integrated circuit is formed; an insulating layer formed on the semiconductor substrate and having a first surface and a second surface which is higher than the first surface; a first electrode formed to avoid the second surface and electrically connected to the inside of the semiconductor substrate; and a second electrode formed on the second surface and electrically connected to the inside of the semiconductor substrate.

Abstract: One of the aspects of the present invention is to provide a power semiconductor device, which includes at least one pair of power modules, each of which has a molding surface covered with molding resin and a radiating surface opposite to the molding surface. Also, the power semiconductor device includes a pair of radiating fins sandwiching the power modules such that the molding surfaces of the power modules contact each other and the radiating surfaces thereof each contact the radiating fins.

Abstract: A semiconductor device has a substrate. A semiconductor die is coupled to a first surface of the substrate. An encapsulate is placed over the semiconductor die. A first plurality of lands is formed on the first surface of the substrate around the encapsulate. A second plurality of lands is formed on a second surface of the substrate. A first group of the second plurality of lands has a pitch and a second group of the second plurality of lands has a pitch of a different length.

Abstract: A system for manufacturing an integrated circuit package system is provided. A dual-type leadframe having first and second rows of leads is formed. A first row of bumps is formed on an integrated circuit chip. Solder paste is placed on the first row of leads, and the first row of bumps is pressed into the solder paste on the first row of leads. The solder paste is reflow soldered to form solder and connect the integrated circuit chip to the first row of leads, and the integrated circuit chip, the first row of bumps, the solder, and the leadframe are encapsulated.

Abstract: An interposer substrate having electrodes on the front surface and on the rear surface thereof, respectively, is prepared, and at least one memory chip having electrodes connected to an internal circuit is prepared. Then, the rear surface of the memory chip is bonded to the front surface of the interposer substrate, and the memory chip is sealed to the front surface of the interposer substrate to constitute an encapsulated capsule type semiconductor package. On the other hand, a logic chip is prepared. Further, a main substrate is prepared in which electrodes are formed on the front surface and on the rear surface, respectively, and desired internal connections are provided between these electrodes.

Abstract: A semiconductor device including: a semiconductor layer; an electrode pad provided above the semiconductor layer; an insulating layer provided above the electrode pad and having an opening which exposes at least part of the electrode pad; and a metal electrode provided at least in the opening and including a first portion provided above the electrode pad, and a second portion provided above part of the insulating layer positioned outside the electrode pad, an area of a top surface of the second portion being larger than an area of a top surface of the first portion.

Abstract: An electronic device includes a die, a first circuit substrate connected to the die, and a second circuit substrate closely coupled to the first circuit substrate. The die is located between the first and second circuit substrates and is protected from tampering by the close coupling of the first and second circuit substrates. The circuit substrates may be circuit carrying elements (e.g. circuit boards) or may be additional die, may be any number of other substrates, and/or may be a combination of substrates. The device may include a cavity such that the die is located in the cavity. The cavity could be formed by any number of means. The device may also include a second die connected to the second substrate such that the first die and second die are located in proximity to each other on opposite sides of the cavity.

Abstract: A transparent conductive multi-layer structure having a smooth base material 1, a transparent conductive layer 2 formed on the smooth base material 1 by coating, an auxiliary electrode layer 3 formed in a pattern on the transparent conductive layer 2, and a transparent substrate 5 joined to the transparent conductive layer 2 and auxiliary electrode layer 3 through an adhesive layer 4. On a smooth peeled-off surface of the transparent conductive layer 2 from which the smooth base material 1 has been peeled off, various devices are formed to set up devices such as a dye-sensitized solar cell and an organic electroluminescent device.

Abstract: A method for protecting an electronic component including a semiconductor chip with a first elastic modulus includes steps as follows. At least one application of a first protective substance is applied on an outer surface of the semiconductor chip. The first protective substance has a second elastic modulus. A second substance is applied to an outer surface of the first protective substance. The second substance has a third elastic modulus. The second elastic modulus is substantially lower than the first elastic modulus and the third elastic modulus, and the first protective substance protects the semiconductor chip from damage during the application of the second substance and/or during the life of the semiconductor chip.

Abstract: The microcavity is delineated by a cover which is formed on a sacrificial layer and in which at least one hole is formed for removal of the sacrificial layer. A plug covers the hole and part of the cover along the periphery of the hole. The plug is made from a material that can undergo creep deformation and can be a polymerized material, in particular selected from photoresists and polyimide, or glass, in particular selected from phosphosilicate glasses. A sealing layer is deposited on the plug and the cover such as to seal the microcavity hermetically. The hole has, for example, a dimension of less than 5 micrometers and is preferably arranged on the highest part of the microcavity. The plug can have a thickness of between 2 and 6 micrometers.

Abstract: A sacrificial substrate for fabricating semiconductor device assemblies and packages with edge contacts includes conductive elements on a surface thereof, which are located so as to align along a street between each adjacent pair of semiconductor devices on the device substrate. A semiconductor device assembly or package includes a semiconductor device, a redistribution layer over an active surface of the semiconductor device, and dielectric material coating at least portions of an outer periphery of the semiconductor device. Peripheral sections of contacts are located on the peripheral edge and electrically isolated therefrom by the dielectric coating. The contacts may also include upper sections that extend partially over the active surface of the semiconductor device. The assembly or package may include any type of semiconductor device, including a processor, a memory device, and emitter, or an optically sensitive device.

Abstract: An electronic package which includes a substrate (e.g., a chip carrier substrate or a PCB), an electronic component (e.g., a semiconductor chip), a heatsink and a thermal interposer for effectively transferring heat from the chip to the heatsink. The interposer includes a compressible, resilient member (e.g., an elastomeric pad) and a plurality of thin, metallic sheets (e.g., copper foils) and the thickness thereof can be adjusted by altering the number of such foils.

Abstract: An integrated antenna type circuit apparatus which provides excellent circuit characteristics while suppressing an increase in packaging area. The integrated antenna type circuit apparatus includes an insulating base, a semiconductor circuit device, chip parts, a molding resin, an antenna conductor, a ground conductor, and external lead electrodes. The plurality of chip parts are mounted on the insulating base, and are soldered to electrodes of wiring conductors on the top of the insulating base for electric and physical connection. The insulating base has a multilayer structure, being formed by laminating a plurality of insulator layers. The antenna conductor is formed on the bottom of the insulating base. A wiring conductor adjacent to the antenna conductor is provided with the ground conductor so that it overlaps with the antenna conductor.

Abstract: A flash memory card and methods of manufacturing same are disclosed. The card includes a semiconductor package fabricated to receive a single-sided or double-sided lid. A surface of the semiconductor package may be formed with holes, trenches and/or pockmarks. After the holes, trenches and/or pockmarks are formed, a lid may be attached to the package surface in an injection molding process. During the injection molding process, the molten plastic flows into the holes, trenches and/or pockmarks to interconnect with the surface of the semiconductor package. Thus, when the molten plastic hardens, the holes, trenches and/or pockmarks ensure that the lid remains firmly attached to semiconductor package.

Abstract: A heat dissipating package structure includes a chip carrier; a semiconductor chip mounted and electrically connected to the chip carrier; a heat spreader having a first surface, an opposed second surface and a hollow structure, the second surface of the heat spreader being mounted on the chip, wherein the chip is larger in size than the hollow structure such that the chip is partly exposed to the hollow structure; an encapsulant formed between the heat spreader and the chip carrier, for encapsulating the chip, wherein the first surface and sides of the heat spreader are exposed from the encapsulant to dissipate heat produced from the chip; and a plurality of conductive elements disposed on the chip carrier, for electrically connecting the chip to an external device. The present invention also provides a method for fabricating the heat dissipating package structure.

Abstract: The generation of an identification number of a chip supporting at least one integrated circuit, including the step of causing a cutting of at least one conductive section by cutting of the chip among several first conductive sections parallel to one another and perpendicular to at least one edge of the chip, the first sections being individually connected, by at least one of their ends, to the chip, and exhibiting different lengths, the position of the cutting line with respect to the chip edge conditioning the identification number.

Abstract: A variety of improved arrangements and processes for packaging integrated circuits are described. More particularly, methods of encapsulating dice in lead frame based IC packages are described that facilitate covering some portions of the bottom surface of the lead frame while leaving other portions of the bottom surface of the lead frame exposed. In some embodiments, a method of encapsulating integrated circuits mounted on a lead frame panel is described. The lead frame panel includes a plurality of leads having associated contacts and supports. A shim having a plurality of cavities is positioned under the lead frame such that the cavities are adjacent to the supports and not adjacent to the contacts. During the encapsulation process, encapsulant material flows under the supports such that the bottom surfaces of the supports are electrically insulated by the encapsulant while the bottom surfaces of the contacts remain exposed.

Abstract: First wirings and first dummy wirings are formed in a p-SiOC film formed on a substrate. A p-SiOC film is formed, and a cap film is formed on the p-SiOC film. A dual damascene wiring, including vias connected to the first wirings and the second wirings, is formed in the cap film and the p-SiOC film 22. Dummy vias are formed on the periphery of isolated vias.

Abstract: A multilayer circuit board is provided that includes at least two insulating layers each sandwiched by circuit layers, thus having at least one internal circuit layer sandwiched by the at least two insulating layers. Via holes are formed in one or more of the insulating layers at the same pitch as bump electrodes of an integrated circuit chip, which permit insertion of the bump electrodes of an integrated circuit chip into the via holes of the multilayer circuit board. Metal films formed within the via holes are electrically connected to at least one of the circuit layers. An internal capacitor may be formed in a predetermined area of an insulating layer and predetermined areas of circuit layers which sandwich the predetermined area of the insulating layer and are opposed to each other. An internal resistor may be formed in an inner circuit layer.

Abstract: A surface mount crystal oscillator comprises a crystal blank, an IC chip having an oscillation circuit integrated thereon, and a hermetic package for accommodating the crystal blank and IC chip therein. The hermetic package comprises a substantially rectangular ceramic substrate formed with a metal film which makes a round on one main surface thereof, and a concave metal cover having an open end face bonded to the metal film. The IC chip is secured to the one main surface of the ceramic substrate through ultrasonic thermo-compression bonding using bumps, the crystal blank is disposed above the IC chip, and the ceramic substrate has the one main surface formed as a flat surface.