Abstract: A copper bonding compatible bond pad structure and associated method is disclosed. The device bond pad structure includes a buffering structure formed of regions of interconnect metal and regions of non-conductive passivation material, the buffering structure providing buffering of underlying layers and structures of the device.

Abstract: An LED package frame includes an LED chip and a heat conductive member made of high heat conductivity material. The heat conductive member has a receiving part at a lateral portion, and is mounted with the LED chip. A lead-coating assembly configured to be inserted into the receiving part of the heat conductive member, including a lead is inserted at one end into the receiving part of the heat conductive member, and electrically connected to the LED chip. An electrically insulating layer is placed in tight contact between the lead and the receiving part of the heat conductive member isolates the lead from the receiving part. With the lead inserted into the heat conductive member, it is possible to reduce size while maintaining high heat conductivity and stability.

Abstract: An integrated circuit apparatus with heat removal has an electrical interconnection network. The electrical interconnection network has a plurality of electrically and thermally conductive vias in electrical communication with terminals of at least one semiconductor device. An electrically insulating heat spreader is chemically bonded to each of the vias at an upper layer of the electrical interconnection network. At the upper layer the vias are electrically isolated from each other. In some embodiments the electrically insulating heat spreader is a polycrystalline diamond body with a metallized undersurface. The metallized undersurface may be etched away between vias.

Abstract: An integrated circuit with an antenna and a method of forming the integrated circuit. The method includes, in an integrated circuit package, forming each bond to or from an integrated circuit pad that is intended to be an antenna connection to be elongated compared to other bonds, and arranged in an approximately perpendicular direction to the plane of the integrated circuit; encapsulating the top of the integrated circuit package with a dielectric material at a height grater than a desired antenna length; and milling the dielectric encapsulation down to a pre-selected and calibrated height, such that the elongated bond wire to/from the integrated circuit pad that is intended to be an antenna connection is severed, such that the approximately vertical bond wire to/from the integrated circuit pad that is intended to be an antenna connection forms a quarter wave monopole.

Abstract: A light emitting diode (LED) package structure including a first substrate, an LED chip, a second substrate, and a thermoelectric cooling device is provided. The first substrate has a first surface and a corresponding second surface. The LED chip suitable for emitting a light is arranged on the first surface of the first substrate, and is electrically connected to the first substrate. The second substrate is below the first substrate, and has a third surface and a corresponding fourth surface. The third surface faces the second surface. The thermoelectric cooling device is arranged between the second surface of the first substrate and the third surface of the second substrate for conducting heat generated by the LED chip during operation.

Abstract: An electronic device (1) has a base plate (2) and an electronics housing (3) connected thereto, with a bonding contact terminal (5). The latter is supported relative to the base plate (2) via a supporting body (6) in such a manner that the supporting body (6) exerts a pre-stressing force onto the bonding contact terminal (5). Due to this support of the bonding contact terminal (5), its position is well defined during the bonding procedure. A secure bond is the result.

Abstract: An assembly and adhesive layer for semiconductor components is arranged between a silicon support (submount) and an electronic functional element for the formation of an electrically-conducting connection between the silicon support and the functional element. The assembly and adhesive layer are arranged on the support. The assembly and adhesive layer are made from a Ti/TiN layer (6), applied to an aluminum contact surface (5) of the silicon support (1), by means of a deposition method. The aluminum contact surface (5) is located on a landing pad (2) on the silicon support (1).

Abstract: A chip card with a chip module having an integrated circuit and, for external contacting, has on a main face a contact zone with a number of contact areas which are spaced apart from one another and are electrically connected to the integrated circuit. At least one contact area is made up of first functional regions with first surfaces and of second functional regions with second surfaces, and the first surfaces of the first functional regions lie higher with respect to the main face than the second surfaces of the second functional regions.

Abstract: An integrated circuit to be cooled may be abutted in face-to-face abutment with a cooling integrated circuit. The cooling integrated circuit may include electroosmotic pumps to pump cooling fluid through the cooling integrated circuits via microchannels to thereby cool the heat generating integrated circuit. The electroosmotic pumps may be fluidically coupled to external radiators which extend upwardly away from a package including the integrated circuits. In particular, the external radiators may be mounted on tubes which extend the radiators away from the package.

Abstract: A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave portion. The first end of the turbulent plate is connected to the frame body, and the second end is lower than the inner lead portions. The chip is fixed under the inner lead portions through the adhesive layer. The bonding wires are connected between the chip and the inner lead portions. The molding compound encapsulates the chip, the bonding wires, and the turbulent plate. The ratio between the thickness of the molding compound over and under the concave portion is larger than 1. The thickness of the molding compound under and over the outer lead portions is not equal.

Abstract: A multidie semiconductor device assembly or package includes an interposer comprising a substrate with at least one receptacle therethrough. A plurality of semiconductor device components (e.g., semiconductor devices) may be assembled with the interposer. For example, at least one contact pad of a semiconductor device component adjacent to one surface of the interposer may be electrically connected to a corresponding contact pad of another semiconductor device component positioned adjacent to an opposite surface of the interposer. As another example, multiple semiconductor device components may be at least partially superimposed relative to one another and at least partially disposed within a receptacle of the interposer.

Abstract: The invention relates to an electronic device comprising: a circuit, comprising a first and a second face, the first face being provided with electrical connection means, a transfer element, comprising a first face and a second face, and being assembled to the second face of the active element through its first face, and comprising electrical connection means on its second face, a connection between the electrical connection means of the active element and the electrical connection means of the transfer element.

Abstract: An electro-optical device includes a substrate that holds an electro-optical material; and a flexible substrate that is connected to the substrate. The flexible substrate has a first connecting portion that is arranged on one surface of the substrate; and a second connecting portion that is arranged on the other surface of the substrate.

Abstract: An electrode plate for an electricity storage and discharge device, which includes a plurality of I/O convergence terminals evenly distributed along a periphery of the electrode plate, and a plurality of conductive structures, each conductive structure for one of the I/O convergence terminals, wherein each conductive structure is of a radial pattern that centers on the one of the I/O convergence terminals, and radiates towards the interior of the electrode plate.

Abstract: In an integrated circuit assembly, know good die (KGD) are assembled on a substrate. Interconnect elements electrically connect pads on a die attached to the substrate to traces or other electrical conductors on the substrate or to pads on another die attached to the substrate. The substrate may have one or more openings, exposing pads of the die. The assembly may comprise one or more dice.

Abstract: The semiconductor device of the present invention includes: first defensive wiring provided above a diffusion isolation layer formed in a substrate or a well, arranged at a minimum wiring pitch allowable in fabrication to cover the diffusion isolation layer; a plurality of signal wiring layers formed above the first defensive wiring; and means for applying a predetermined signal to the first defensive wiring and capturing a change in an electrical or physical property of the first defensive wiring.

Abstract: A wiring substrate 20, comprising a glass substrate, formed by integrally bundling a plurality of glass fibers and provided with through holes 20c, and conductive members 21, disposed at through holes 20c, is used. Input portions 21a of conductive members 21, formed on an input surface 20a of this wiring substrate 20, are connected to bump electrodes 17, which are provided on an output surface 15b of a PD array 15 in one-to-one correspondence with respect to conductive members 21, thereby arranging a semiconductor device 5. A radiation detector is arranged by connecting a scintillator 10 via an optical adhesive agent 11 to a light-incident surface 15a of PD array 15 and connecting a signal processing element 30 via bump electrodes 31 to output surface 20b of wiring substrate 20. A semiconductor device, with which the semiconductor elements and the corresponding conductive paths of the wiring substrate are connected satisfactorily, and a radiation detector using this semiconductor device are thus provided.

Abstract: A cooling system of a power semiconductor module of the invention includes a temperature detection sensor provided in a semiconductor element as a heat source provided in a power semiconductor module, and a controller which estimates a change of a heat transfer coefficient from the power semiconductor module to cooling water based on output information Tj of the temperature detection sensor and drive output information Sr of a rotation speed detection sensor for a pump motor to drive a cooling pump, controls the pump motor according to this estimated result, and controls cooling capacity of the cooling water.

Abstract: An apparatus and method of integrating optics into an IC package is for detecting light from at least one light source is disclosed. The apparatus has a housing, which has a predetermined spectral transmittance. A sensor is positioned within the housing. An opaque mask is applied to the housing, where the opaque mask has a hole aligned with the sensor such that the light's centroid is detected by the sensor. In one embodiment, the apparatus further comprises a substrate for positioning and stabilizing the sensor in the housing, an analog filter and amplification module (“AFA”) for filtering and amplifying signals from the sensor and generating a second signal, and a digital signal processor (“DSP”) for generating a coordinate system by extracting frequency components from the AFA output signal.

Abstract: A package substrate for a multi-package module. The package substrate comprises a substrate having a die region and at least one thermal channel region outwardly extending to an edge of the substrate from the die region. An array of bumps is arranged on the substrate except in the die and thermal channel regions, in which the interval between the bumps is narrower than the width of the thermal channel region. An electronic device with a package substrate is also disclosed.