Patents Examined by Chris Chu
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Patent number: 8975757Abstract: Solder used for flip chip bonding inside a semiconductor package was a Sn—Pb solder such as a Pb-5Sn composition. Lead-free solders which have been studied are hard and easily form intermetallic compounds with Sn, so they were not suitable for a flip chip connection structure inside a semiconductor package, which requires stress relaxation properties. This problem is eliminated by a flip chip connection structure inside a semiconductor package using a lead-free solder which is characterized by consisting essentially of 0.01-0.5 mass percent of Ni and a remainder of Sn. 0.3-0.9 mass percent of Cu and 0.001-0.01 mass percent of P may be added to this solder composition.Type: GrantFiled: March 3, 2009Date of Patent: March 10, 2015Assignee: Senju Metal Industry Co., Ltd.Inventors: Minoru Ueshima, Masayuki Suzuki, Yoshie Yamanaka, Shunsaku Yoshikawa, Tokuro Yamaki, Tsukasa Ohnishi
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Patent number: 8975176Abstract: The amount of gold required for bonding a semiconductor die to an electronic package is reduced by using a sheet preform tack welded to the package prior to mounting the die. The preform, only slightly larger than a semiconductor die to be attached to the package, is placed in the die bond location and tack welded to the package at two spaced locations.Type: GrantFiled: March 12, 2014Date of Patent: March 10, 2015Assignee: Materion CorporationInventor: Ramesh Kothandapani
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Patent number: 8970023Abstract: A semiconductor device includes a first die having a first active surface and a first backside surface opposite the first active surface, a second die having a second active surface and a second backside surface opposite the second active surface, and an interposer, the first active surface of the first die being electrically coupled to a first side of the interposer, the second active surface of the second die being electrically coupled to a second side of the interposer. The semiconductor device also includes a first connector over the interposer, a first encapsulating material surrounding the second die, the first encapsulating material having a first surface over the interposer, and a via electrically coupling the first connector and the interposer. A first end of the via is substantially coplanar with the first surface of the first encapsulating material.Type: GrantFiled: February 4, 2013Date of Patent: March 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bruce C. S. Chou, Chih-Hsien Lin, Hsiang-Tai Lu, Jung-Kuo Tu, Tung-Hung Hsieh, Chen-Hua Lin, Mingo Liu
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Patent number: 8963324Abstract: In a semiconductor device, a semiconductor module is pressed against a cooler by a spring member. The spring member is compressed by a beam member that is connected with a strut fixed to the cooler. The cooler has a pressed part in which the semiconductor module is pressed, and a strut fixing part to which the strut is fixed. The strut fixing part has higher rigidity than the pressed part.Type: GrantFiled: March 26, 2014Date of Patent: February 24, 2015Assignee: Toyota Jidosha Kabushiki KaishaInventors: Takato Sato, Yukio Onishi, Hiroyuki Kono, Hiroaki Yoshizawa, Toshio Watari, Hiromi Yamasaki
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Patent number: 8963331Abstract: Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel is formed to extend across both the barrier and the component. The barrier may extend around an entire lateral periphery of the component, and may be spaced from the component by an intervening ring of electrically insulative material. The copper component may be a bond pad or an interconnect between two levels of metal layers. Some embodiments include semiconductor constructions in which nickel extends across a copper component, a copper barrier is laterally offset from the copper component, and an insulative material is between the copper barrier and the copper component.Type: GrantFiled: April 30, 2014Date of Patent: February 24, 2015Assignee: Micron Technology, Inc.Inventors: Tianhong Zhang, Akram Ditali
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Patent number: 8953117Abstract: A waterproof user interface panel includes an electronic display assembly having a touch sensitive surface for activation of touch switches, and a housing including a cutout area. A protective film is disposed over the assembly and secured to the housing. The housing includes a top surface, a bottom surface and a peripheral sidewall to define a housing cavity. Sealing material covers the bottom surface, with a void between the top surface of the sealing material and the electronic display assembly. A vent is provided between the void and the external environment to allow air to pass. A filter may be positioned in the vent to prevent the passage of water droplets through the filter while allowing the passage of air and water vapor.Type: GrantFiled: October 5, 2012Date of Patent: February 10, 2015Assignee: Balboa Water Group, Inc.Inventors: Paul Rosenau, Tony Pipitone, Jerrell P. Hollaway
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Patent number: 8945992Abstract: A metal tab die attach paddle (DAP) disposed between the lead frame and a power device die in a power device package reduces the stress exerted on the semiconductor power device die caused by the different coefficients of thermal expansion (CTE) of the semiconductor power device die and the lead frame. In addition the power device package substantially prevents impurities from penetrating into the power device package by increasing the surface creepage distance of a sealant resulting from the metal tab DAP and an optional swaging of the lead frame.Type: GrantFiled: October 21, 2011Date of Patent: February 3, 2015Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Joon-seo Son, O-seob Jeon, Taek-keun Lee, Byoung-ok Lee
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Patent number: 8941247Abstract: In a packaging structure for a microelectromechanical-system (MEMS) resonator system, a resonator-control chip is mounted on a lead frame having a plurality of electrical leads, including electrically coupling a first contact on a first surface of the resonator-control chip to a mounting surface of a first electrical lead of the plurality of electrical leads through a first electrically conductive bump. A MEMS resonator chip is mounted to the first surface of the resonator-control chip, including electrically coupling a contact on a first surface of the MEMS resonator chip to a second contact on the first surface of the resonator-control chip through a second electrically conductive bump. The MEMS resonator chip, resonator-control chip and mounting surface of the first electrical lead are enclosed within a package enclosure that exposes a contact surface of the first electrical lead at an external surface of the packaging structure.Type: GrantFiled: February 27, 2014Date of Patent: January 27, 2015Assignee: SiTime CorporationInventors: Pavan Gupta, Aaron Partridge, Markus Lutz
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Patent number: 8921996Abstract: A power module substrate includes: a ceramics substrate having a surface; and a metal plate connected to the surface of the ceramics substrate, composed of aluminum, and including Cu at a joint interface between the ceramics substrate and the metal plate, wherein a Cu concentration at the joint interface is in the range of 0.05 to 5 wt %.Type: GrantFiled: September 16, 2013Date of Patent: December 30, 2014Assignee: Mitsubishi Materials CorporationInventors: Yoshirou Kuromitsu, Yoshiyuki Nagatomo, Takeshi Kitahara, Hiroshi Tonomura, Kazuhiro Akiyama
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Patent number: 8921995Abstract: An integrated circuit (IC) package is disclosed comprising a substrate including a plurality of substrate contacts; a semiconductor die including a plurality of die contacts; and a plurality of conductors for providing direct connections between substrate contacts and die contacts, respectively. By having the conductors directly route the connections between the die contacts and substrate contacts, many improvements may be realized including, but not limited to, improved package routing capabilities, reduced die and/or package size, improved package reliability, improved current handling capacity, improved speed, improved thermal performance, and lower costs.Type: GrantFiled: July 15, 2011Date of Patent: December 30, 2014Assignee: Maxim Intergrated Products, Inc.Inventors: Tarak A. Railkar, Steven D. Cate
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Luminescence concentrators and luminescence dispersers on the basis of oriented dye zeolite antennas
Patent number: 8917969Abstract: A luminescence concentrator (LK) may concentrate both incident direct and diffuse light by way of frequency shift and total internal reflection. It differs fundamentally from geometric concentrators. With sufficient geometric expansion of the collector plate, nearly arbitrarily high concentration can be achieved in the LK. A luminescence disperser is an apparatus which holds both directional and nondirectional incident light captive in a transparent body by way of frequency shift and total internal reflection and emits it diffusely or directionally uniformly distributed across an area by way of luminescence emission. The object of the invention is a method for the technical implementation of the LK and luminescence disperser, using zeolite crystals having a nanotube structure, into which the luminescent dyes are embedded such that they have antenna properties. Using the resulting novel structures, problems can be solved which made the technical use of LK impossible or at least considerably limited it.Type: GrantFiled: March 31, 2009Date of Patent: December 23, 2014Assignees: Universität ZürichInventors: Gion Calzaferri, Andreas Kunzmann, Dominik Brühwiler, Christophe Bauer -
Patent number: 8916979Abstract: An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring.Type: GrantFiled: February 7, 2013Date of Patent: December 23, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hao Tsai, En-Hsiang Yeh, Chuei-Tang Wang
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Patent number: 8907493Abstract: A first through hole 16 and a second through hole 17 are formed which penetrate from a rear surface 10a side of an element formation surface 10b of a semiconductor substrate (silicon substrate 10) in which an element section Ra is formed, to the element formation surface. An outer circumference insulation film 12 is formed on the side wall of the bottom of the second through hole 17 to surround the outer circumference of the second through hole 17 having a larger opening diameter among these through holes.Type: GrantFiled: February 7, 2013Date of Patent: December 9, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kengo Uchida, Kazuyuki Higashi
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Patent number: 8907500Abstract: A microelectronic package can include a substrate having first and second opposed surfaces extending in first and second transverse directions and an opening extending between the first and second surfaces and defining first and second distinct parts each elongated along a common axis extending in the first direction, first and second microelectronic elements each having a front surface facing the first surface of the substrate and a column of contacts at the respective front surface, a plurality of terminals exposed at the second surface, and first and second electrical connections aligned with the respective first and second parts of the opening and extending from at least some of the contacts of the respective first and second microelectronic elements to at least some of the terminals. The column of contacts of the first and second microelectronic elements can be aligned with the respective first and second parts of the opening.Type: GrantFiled: February 4, 2013Date of Patent: December 9, 2014Assignee: Invensas CorporationInventors: Belgacem Haba, Wael Zohni
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Patent number: 8907472Abstract: A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS.Type: GrantFiled: February 7, 2013Date of Patent: December 9, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Wensen Hung
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Patent number: 8901713Abstract: A structure is provided in which the back gate regions are physically separated from one another as opposed to using reversed biased pn junction diodes. In the present disclosure, the back gate regions can be formed first through a buried dielectric material of an extremely thin semiconductor-on-insulator (ETSOI) substrate. After dopant activation, standard device fabrication processes can be performed. A semiconductor base layer portion of the ETSOI substrate can then be removed from the original ETSOI to expose a surface of the back gates.Type: GrantFiled: November 15, 2012Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
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Patent number: 8901743Abstract: A method of fabricating a semiconductor device includes forming a first insulation film over a semiconductor substrate, the semiconductor substrate including an outer region and an inner region located at an inner side of the outer region, forming a first wiring over the first insulation film in the inner region, forming a second insulation film over the first wiring and over the first insulation film, decreasing a film thickness of the second insulation film in the inner region with regard to a film thickness of the second insulation film in the outer region, and polishing the second insulation film after the decreasing of the film thickness of the second insulation film.Type: GrantFiled: January 8, 2013Date of Patent: December 2, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Tomiyasu Saito, Tatsuya Mise, Hiromichi Ichikawa, Tetsuya Takeuchi, Genshi Okuda
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Patent number: 8896134Abstract: The film for back surface of flip-chip semiconductor according to the present invention is a film for back surface of flip-chip semiconductor to be formed on a back surface of a semiconductor element having been flip-chip connected onto an adherend, wherein a tensile storage elastic modulus at 23° C. after thermal curing is 10 GPa or more and not more than 50 GPa. According to the film for back surface of flip-chip semiconductor of the present invention, since it is formed on the back surface of a semiconductor element having been flip-chip connected onto an adherend, it fulfills a function to protect the semiconductor element. In addition, since the film for back surface of flip-chip semiconductor according to the present invention has a tensile storage elastic modulus at 23° C. after thermal curing of 10 GPa or more, a warp of the semiconductor element generated at the time of flip-chip connection of a semiconductor element onto an adherend can be effectively suppressed or prevented.Type: GrantFiled: April 18, 2011Date of Patent: November 25, 2014Assignee: Nitto Denko CorporationInventors: Naohide Takamoto, Goji Shiga
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Patent number: 8896127Abstract: An integrated circuit structure includes a semiconductor substrate and a hard mask layer formed on the semiconductor substrate. The integrated circuit structure further includes at least a conductive layer formed in the hard mask layer and a via extending from the hard mask layer to at least a portion of the semiconductor substrate, wherein the via has a round corner and a tapered sidewall.Type: GrantFiled: November 8, 2012Date of Patent: November 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Pin Chang, Wen-Chih Chiou, Chen-Hua Yu
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Patent number: 8896116Abstract: A microelectronic package includes a substrate (110), a die (120) embedded within the substrate, the die having a front side (121) and a back side (122) and a through-silicon-via (123) therein, build-up layers (130) built up over the front side of the die, and a power plane (140) in physical contact with the back side of the die. In another embodiment, the microelectronic package comprises a substrate (210), a first die (220) and a second die (260) embedded in the substrate and having a front side (221, 261) and a back side (222, 262) and a through-silicon-via (223, 263) therein, build-up layers (230) over the front sides of the first and second dies, and an electrically conductive structure (240) in physical contact with the back sides of the first and second dies.Type: GrantFiled: January 8, 2013Date of Patent: November 25, 2014Assignee: Intel CorporationInventors: Ravi K. Nalla, Mathew J. Manusharow, Drew W. Delaney