Abstract: A semiconductor device has a gate electrode formed on P type semiconductor substrate through a gate insulation film, a low concentration N− type drain region formed so as to be adjacent to the gate electrode, a high concentration N+ type drain region separated from the other end of said gate electrode and included in said low N− type drain region, and a middle concentration N type layer having high impurity concentration peak at a position of the predetermined depth in said substrate at a region spanning at least from said gate electrode to said high concentration N+ type drain region, and formed so that high impurity concentration becomes low at a region near surface of the substrate.

Abstract: A method of manufacture reduces costs and provides an excellent mass-productivity, a super-junction semiconductor device, that facilitates reducing times of heat treatment of the alternating conductivity type layer subjects, and preventing the characteristics of the alternating conductivity type layer from being impaired. A surface MOSFET structure, including p-type base regions, p+-type contact region in p-type base region, an n+-type source region in p-type base region, a gate electrode layer and a source electrode, is formed in the surface portion of an n-type semiconductor substrate through the usual double diffusion MOSFET manufacturing process. An oxide film is deposited by the CVD method on the back surface of the semiconductor substrate, a resist mask for defining p-type partition regions is formed on the oxide film, oxide film is removed by ion etching, and trenches are dug.

Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.

Abstract: A thin film transistor and a method of manufacturing the same includes forming a copper alloy line on substrate, an oxidation film formed on the upper surface of the copper alloy line. The copper alloy line includes a concentration y of magnesium, and the copper alloy line has a thickness t. the concentration y of magnesium in copper alloy line is related to the thickness is as follows: y ≤ 94 t .

Abstract: A method for fabricating a semiconductor device, involving: forming a gate stack on a substrate; depositing a material layer on the gate stack; etching the material layer, thereby forming a dielectric capsulate layer on the gate stack; forming a pair of shallow source/drain extensions in a first region of the substrate by implanting a plurality of first dopant ions at a tilt angle with a horizontal offset defined by a thickness of the dielectric capsulate layer; and forming at least one spacer on the dielectric capsulate layer; forming deep source/drain contact junctions in a second region of the substrate by vertically implanting a plurality of second dopant ions below the first region with no tilt and with a horizontal offset defined by a thickness of the at least one spacer.

Abstract: The invention relates to a fuse layout structure in a laser fuse box of a semiconductor integrated circuit and a method for fabricating the same. In one example of the invention, the fuse layout structure in a laser fuse box of the semiconductor integrated circuit includes a plurality of fuses with the central regions thereof extending parallel to each other within the fuse box, and the central regions of the fuses being covered with an insulative protection layer. Thus, the fuse layout structure of the present invention occupies a minimum area in the chip while minimizing influences of the heat generated by fusing neighboring fuses.

Abstract: A semiconductor device includes sidewall insulating films formed on sides of the gate electrode layer respectively facing source and drain regions, and silicide layers formed on the source and drain regions. Oxygen-introduced portions are respectively formed in the source and drain regions near the sidewall insulating films. The oxygen-introduced portions contain oxygen atoms that are locally distributed on the interfaces between the silicide layers and the silicon layers of the source or drain regions at a concentration of 4.5×1019 cm−3 or more and an areal density of 5×1013 cm−2 or more. The oxygen-introduced portions form an Ohmic contact between the silicide layers and the silicon layers of the source or drain regions.

Abstract: A process for fabrication of a semiconductor device including a modified ONO structure, including forming the modified ONO structure by providing a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; depositing a layer comprising a high-K dielectric material on the first oxide layer; and forming a top oxide layer on the layer comprising a high-K dielectric material. The semiconductor device may be, e.g., a MIRRORBIT™ two-bit EEPROM device or a floating gate flash device including a modified ONO structure.

Abstract: A process for constructing a trench MOS-gated device includes: forming in a semiconductor substrate an extended trench that comprises an upper segment and a bottom segment, wherein the bottom segment has a lesser width relative to a greater width of the trench upper segment and extends to a depth corresponding to the total depth of the extended trench. The bottom segment of the trench is substantially filled with dielectric material. The trench upper segment has a floor and sidewalls comprising dielectric material and is substantially filled with a conductive material to form a gate region. A heavily doped source region of the first conduction type and a heavily doped body region of the second conduction type are formed in a surface well region on the side of the extended trench opposite an extended doped zone.

Abstract: A phase change memory may have reduced reverse bias current by providing a N-channel field effect transistor coupled between a bipolar transistor and a conductive line such a row line. By coupling the gate of the MOS transistor to the row line, reverse bias current in unselected cells or in the standby mode may be reduced.

Abstract: An underfilling method for a flip-chip packaging process includes coating a underfill material layer over bumps on a semiconductor substrate, performing a die sawing process on the semiconductor substrate to from a number of dies, and performing a flip-chip process on each of the dies to adhere each of the dies to another substrate. Because the underfill material is coated from the top of the bumps, the air-trapping problem can be eliminated. The process time is shortened to improve yield because the underfill material is dispensed over all the dies before the die-sawing process. This is different from the conventional underfilling process, which has to dispense underfill material and seal edges on each individual die.

Abstract: A method of implanting dopants into a semiconductor structure wherein a lateral periphery of a photoresist mask is shifted after implanting a first dopant and prior to implanting a second dopant. The invention also includes semiconductor structures having two doped regions of a semiconductive material separated by a region less heavily doped than the doped regions.

Abstract: A low heat loss and small contact area electrode structure for a phase change media memory device is described. The memory device includes a composite electrode that includes a dielectric mandrel that is connected with a substrate and having a tapered shape that terminates at a vertex. An electrically conductive material conformally covers the dielectric mandrel and terminates at a tip. A first dielectric layer covers all of the composite electrode except an exposed portion of the composite electrode that is adjacent to the tip. A phase change media is in contact with the exposed portion. The exposed portion is only a small percentage of an overall surface area of the composite electrode so that a contact footprint between the exposed portion and the phase change media is small relative to a surface area of the phase change media and Joule heat transfer from the phase change media into the composite electrode is reduced.

Abstract: The invention relates to a semiconductor device comprising a substrate (1) comprising for instance silicon with thereon a layer (2, 4) comprising at least organic material which contains a passage (6, 8) to the substrate (1). The passage (6,8) has walls (7, 9) transverse to the layer (2, 4). A metal layer (11) is applied on the substrate (1) in at least that portion which adjoins the passage (8). The organic material forming the walls (7, 9) of the passage (6, 8) is covered with an oxide liner (12), and the passage (6, 8) is filled with a metal (14). According to the invention, a metal liner (13) comprising Ti or Ta is provided between the oxide liner (12) and the metal (14) filling the passage (6, 8). It is achieved by this that the device has a better barrier between the organic material (2, 4) and the interconnection metal (14) and that the organic material (2, 4) has a better protection during the various steps of the process.

Abstract: A method of manufacturing a semiconductor device (10) including a semiconductor element (1), such as a transistor, which is provided, on the rear side, with a conductive layer (3) including gold, and which is attached, on said side, to a conductive plate (2), such as a lead frame (2), by way of a silver-containing organic matrix (4) which is thermally cured. Subsequently, the element (1) is connected to the plate (2) by way of wire connectors (5) and provided with an encapsulation (6). The silver paste (4) is cured at a temperature of at least 350° C., preferably approximately 400° C. In this way, an excellent adhesion of the element (1) to the plate (2) is obtained, enabling the wired connectors (5) to be subsequently provided by way of wire bonding without elements (1) becoming detached from the plate (2). Moreover, the connection is still sufficiently flexible to deal with a difference in thermal expansion between the element (1) and the plate (2), even if the latter is made of copper.

Abstract: A metal gate structure and method of forming the same employs an etch stop layer between a first metal layer, made of TiN, for example, and the metal gate formed of tungsten. The etch stop layer prevents overetching of the TiN during the etching of the tungsten in the formation of the metal gate. The prevention of the overetching of the TiN protects the gate oxide from undesirable degradation. The provision of aluminum or tantalum in the etch stop layer allows a thin etch stop layer to be used that provides adequate etch stopping capability and does not undesirably affect the work function of the TiN.

Abstract: A memory integrated circuit having three layers of metallic traces disposed over a substrate assembly including various active devices. The traces are arranged to include I/O traces that are continuous in the third layer across spans of 4 or 8 memory blocks of an array, and that are interspersed on the third layer with non-I/O lines adapted to reduce interference between I/O lines. Column select lines, orthogonal to I/O lines and disposed in the third layer of metallic traces, except in the vicinity of I/O lines, are provided in a linear configuration and shielded from parallel digit lines in the first layer of traces by traces of the intervening second layer of traces. Global bleeder lines disposed in the third layer of traces are adapted to apply a standby voltage to a plurality of sense amplifiers. Other features of the invention include two layer power and ground bus traces, and row decoder and phase driver circuits disposed in throat and gap cell regions respectively.

Abstract: A light emitting device formed of a substrate having first and second regions, a first non-transparent electrode formed on the substrate in the first region, a layer of organic light emitting material provided over the first non-transparent electrode in the first region, a layer of organic light emitting material provided over the substrate in the second region, the light emitting materials each having at least one planar surface which is corrugated, a second non-transparent electrode formed over the light emitting material in the first region, and a mirror formed over the light emitting material in the second region. A device having a stacked structure of electrodes and light emitting layers is also disclosed, as are various methods of fabricating the devices.

Abstract: Two types of topologically different three-dimensional integrated circuits (for example a 4-layer three-dimensional memory array and an 8-layer three-dimensional memory array) are fabricated from a single set of photolithographic masks. In one example, masks 1-5 are used along with other masks to create the first four levels of memory cells in both a 4-layer memory array and an 8-layer memory array. The 8-layer memory array is completed with masks used to form the top four layers of the array. An integrated circuit identification circuit generates an appropriate circuit identification signal for both types of integrated circuits by sensing whether a conductive path across some or all of the device levels of the integrated circuit is continuous, and then by selecting the appropriate circuit identification signal.

Abstract: A flip-chip-type device is formed from a plurality of flip-chip semiconductor device units integrated together on a common substrate having a Group III nitride compound semiconductor layer. A sealing resin is laminated on a surface of the common substrate cured, and the substrate is then divided into individual sealed flip-chip semiconductor devices. Because the positive and negative electrodes are formed on the same side of the devices, the sealing resin need only be applied to the side of the substrate on which the electrodes are formed. Metal pillars may be formed on the electrodes and extend through the cured resin to electrically connect the flip-type semiconductor device to an external source and produce a self-contained package.