Abstract: A method of transmitting data determines a measure of consecutive packet loss in a network; a ratio of a number of data packets and a number of error correction packets is selected in dependence on the measure. A stream of data packets is generated, and a stream of error correction packets is generated in dependence on the stream of data packets such that the proportion of error correction packets generated to the data packets generated is commensurate with the selected ratio.

Abstract: Certain embodiments of the present invention involve a method of storing an erasure coded copy of block data, and storing newly updated block data into a separate erasure-coded log structure. The method also includes auditing both the erasure copy of block data and the newly updated block data. The erasure copy of block data and the newly updated block data are probabilistically checked during the audit. In certain other embodiments the newly updated block data is stored in a log structure.

Abstract: A data generation device 101 transmits communication data bound for a data receiving device 105 from a transmission unit, and a monitoring device 103 receives the communication data. The monitoring device 103 requests retransmission of the communication data to the data generation device 101, and the data generation device 101 retransmits the communication data from a retransmission unit being different from the transmission unit. The monitoring device 103 receives retransmission data retransmitted from the retransmission unit, compares the communication data with the retransmission data. If the communication data and the retransmission data are identical, the monitoring device 103 transmits the communication data to the data receiving device 105. If the communication data and the retransmission data are not identical, the monitoring device 103 transmits a message which notifies that the communication data and the retransmission data are not identical to the data generation device 101.

Abstract: In a system and method for streaming data, the system includes: instructions that: encode a data stream at a first bitrate; transmit a plurality of first data blocks to a receiver, each of the first data blocks including: a first source packet corresponding to the encoded data stream; and a first repair packet; and transmit a plurality of second data blocks to the receiver for a first predetermined period of time, each of the second data blocks including: a second source packet corresponding to the encoded data stream; a second repair packet; and a probing packet.

Abstract: Server computers often include one or more input/output (I/O) devices for communicating with a network or direct attached storage device. Data written to or read from storage devices may acquire errors in transit. The I/O adapter device may implement processes to generate or check error correction values, where the error correction values are provided to verify the correctness of the written or read value. The I/O adapter device may determine the portion of the data to be used in calculating the error correction value in a flexible and configurable manner.

Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.

Abstract: A method for operating a RAID storage system includes configuring the RAID storage devices to receive in a read or write command a byte count, receiving a first data block to write to the storage system, compressing the received first data block to generate a first compressed data block, and then storing the first compressed data block memory. The method additionally includes executing a set of RAID operations to perform a partial stripe update, including: retrieving a second compressed data block from memory; determining a physical size of the second compressed data block; generating, based on the second compressed data block and the physical size, redundant data corresponding with the second compressed data block; and writing the second compressed data block and the redundant data by transmitting a write command including the second compressed data block, the redundant data, and the physical size to the set of RAID storage devices.

Abstract: Described herein is a method implemented by circuitry for providing fault tolerance in a combinational circuit. The circuitry identifies sensitive gates of the circuit that require protection from at least one of a first type of fault and a second type of fault. Further, circuitry computes for each first type of transistor included in the sensitive gate, a first failure probability, and for each second type of transistor included in the sensitive gate, a second failure probability. The circuitry calculates a first parameter corresponding to a number of the first type of transistors for which the computed first failure probabilities exceed a first predetermined threshold and a second parameter corresponding to a number of second type of transistors for which the computed second failure probabilities exceed a second predetermined threshold to determine a protection type based on an area overhead constraint.

Abstract: Systems and methods described herein provides a method for dynamically allocating an iteration number for a decoder. The method includes receiving, at an input buffer, an input signal including at least one data packet. The method further includes calculating a first iteration number for decoding the at least one data packet. The method further includes monitoring at least one of available space of the input buffer and available decoding time for the at least one data packet. The method further includes dynamically adjusting the first iteration number to a second iteration number based on the available space or the available decoding time to continue decoding the at least one data packet.

Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The memory generally comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to generate a set of converted log likelihood ratios by scaling a set of original log likelihood ratios using a selected scalar value, wherein the controller determines the selected scalar value by generating a plurality of sets of scaled log likelihood ratios by scaling the set of original log likelihood ratios with a plurality of corresponding scalar values, calculating a plurality of respective correlation coefficients each measuring a similarity of a respective set of scaled log likelihood ratios to the set of original log likelihood ratios, and selecting the scalar value corresponding to the set of scaled log likelihood ratios whose respective correlation coefficient is highest as the selected scalar value.

Abstract: A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.

Abstract: Systems and methods for error correction in structured light are disclosed. In one aspect, a method includes receiving, via a receiver sensor, a structured light image of at least a portion of a composite code mask encoding a plurality of codewords, the image including an invalid codeword. The method further includes detecting the invalid codeword. The method further includes generating a plurality of candidate codewords based on the invalid codeword. The method further includes selecting one of the plurality of candidate codewords to replace the invalid codeword. The method further includes generating a depth map for an image of the scene based on the selected candidate codeword. The method further includes generating a digital representation of a scene based on the depth map. The method further includes outputting the digital representation of the scene to an output device.

Abstract: Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one. In yet another aspect, rank-modulation rewriting schemes which take advantage of polar codes, are provided for use with flash memory.

Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.

Abstract: A control device stores information associating each of a plurality of physical areas with a plurality of logical areas. The control device respectively stores a plurality of first user data included in a first stripe and a first parity data created on the basis thereof in each of the plurality of physical areas, and, in accordance with receiving a write request for updated user data that updates the user data, which is stored in a first physical area, for a first logical area associated with the first physical area, creates a second parity data on the basis of a data group formed using the updated user data and a plurality of second user data that differs from the plurality of first user data.

Abstract: A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.

Abstract: The method is used for detection and/or removal of errors in transmission systems which comprise a transmitter unit and at least one receiver unit. The transmitter unit transmits to the receiver unit on a semi-persistent transmission resource which provides an adjustable frequency range and an adjustable time period. Furthermore, the self-repeating, semi-persistent transmission resource repeating with the period TSPS is rigidly assigned to the receiver unit. Following this, at least one but not all of the HARQ process numbers available for the self-repeating, semi-persistent transmission resource are reserved for the latter.

Abstract: Automatic Repeat Request (ARQ) protocol is used in many modern telecommunication systems for improved link level reliability. Hybrid ARQ (HARQ) protocol takes advantage of the retransmissions in ARQ to enable the receiver to decode the currently received data by combining it with all the previously received transmissions that were not successfully decoded. Each successive retransmission improves the probability of correctly decoding the data. To support HARQ, the receiver is required to store the previously received unsuccessful transmissions for combining with future retransmissions. The storage of the previously received unsuccessful transmissions can be very large depending on type of the HARQ protocol used. A method and apparatus are disclosed that enable reduced memory storage requirements while maintaining the HARQ performance requirements. The reduced memory requirements result in reduced cost, reduced power consumption and lowered cost.

Abstract: Various embodiments of methods and systems for bit flip identification for debugging and/or power management in a system on a chip (“SoC”) are disclosed. Exemplary embodiments seek to identify bit flip occurrences near in time to the occurrences by checking parity values of data blocks as the data blocks are written into a memory component. In this way, bit flips occurring in association with a write transaction may be differentiated from bit flips occurring in association with a read transaction. The distinction may be useful, when taken in conjunction with various parameter levels identified at the time of a bit flip recognition, to debug a memory component or, when in a runtime environment, adjust thermal and power policies that may be contributing to bit flip occurrences.

Abstract: This invention provides a cyclically-coupled (CC-) quasi-cyclic (QC-) low-density parity-check (LDPC) code and its decoder architecture. The essence of the invention is to introduce the convolutional nature to a plurality of individual block codes internally so as to form a resultant block code with a prolonged code length while slightly increasing the hardware complexity in decoder realization. The CC-QC-LDPC code is formed by cyclically coupling a plurality of sub-codes each being a QC-LDPC code such that overlapping of some variable nodes between two consecutive sub-codes results. The decoder comprises plural sub-decoders each configured to decode the channel messages for one sub-code. The sub-decoders are arranged in a ring shape such that an individual sub-decoder is configured to communicate edge messages with two neighboring sub-decoders adjacent to said individual sub-decoder in the decoding of the channel messages.