Abstract: A system for performing a scan test on an integrated circuit such as a System on a Chip (SoC) that may be packaged in different package types and with different features enabled includes a bypass-signal generator and a first scan-bypass circuit. The bypass-signal generator generates a first bypass signal based on chip package information. The first bypass signal indicates whether a first scan chain associated with a first non-common circuit block of the SoC is to be bypassed. The first scan chain is bypassed in response to the first bypass signal. By enabling partial scan testing based on package information, unintentional yield loss caused by a full scan test determining an SoC is faulty can be avoided.

Abstract: Method for testing a memory under test (1) including a plurality of memory cells and a Memory Built-In Self-Test Engine (2) connectable to a memory under test. The MBIST engine (2) is arranged to generate appropriate addressing and read and/or write operations to the memory under test (1). The MBIST engine (2) is connected to a March Element Stress register (MESR) (3), a generic march element register (GMER) (4), and a Command Memory (5). The GMER (4) specifies one of a set of Generic March Elements (GME), and the MESR (3) specifies the stress conditions to be applied. Only a few GMEs are required in order to specify most industrial algorithms. The architecture is orthogonal and modular, and all speed related information is contained in the GME. In addition, only little memory is required for the specification of the test, providing a low implementation cost, yet with a high flexibility.

Abstract: A scan test circuit includes: a functional path, including: a D-type latch, for receiving an input and generating an output, the D-type latch including a feedback node; and a test path, including: a scan latch, for receiving a test input and generating an output. The scan test circuit also includes a tri-state inverter. The output of the test path is input to the feedback node of the D-type latch and also input to the tri-state inverter. The functional path is clocked by pulses generated by a pulse generator according to a system clock. The test path is clocked by a test clock generated according to a test enable signal and the system clock. When the test enable signal is enabled, the generation of the pulses is disabled.

Abstract: In an arrangement of the disclosed systems, devices, and methods, a matrix representation of a block code comprising m bit-planes is obtained, a generator matrix corresponding to each of the m bit-planes from the matrix representation is extracted, a transformed generator matrix and a transformed data symbol vector for the first bit-plane of the block code are determined, a reverse-mapped transformed generator matrix for each of the second bit-plane through the mth bit-plane of the block code are determined, and instructions for the encoder architecture based on the transformed generator matrix for the first bit-plane and the reverse-mapped transformed generator matrix for each of the second bit-plane through the mth bit-plane of the block code are generated.

Abstract: A device includes a controller configured to provide a data word and check bits for the data word to decoding logic, the decoding logic configured to generate a decoding of the data word and check bits for the data word in conformance with an H-matrix having the following properties: (a) no all 0 columns; (b) all columns are distinct; (c) no linear dependency involving three or less columns; (d) no linear dependency involving columns Ci, Cj, Ck, Cm, where m>k>j>i, where j=i+1 and m=k+1; and (e) no linear dependency involving columns Ci, Cj, Ck, Cm, where m>k>j>i, where (j=i+1 and m?k=q) or (k=j+1 and m?i=q) or (m=k+1 and j?i=q) for all integer values of q such that q>1 and q<=d, where d>=2 and d<=n?1 where n?k is a number of the check bits.

Abstract: A non-volatile semiconductor memory device includes: a memory unit including a plurality of memory cells, each of the plurality of memory cells to perform a multi-level storage operation by assigning a value including a plurality of bits to at least four data states defined according to a threshold level; and a controller to control the memory unit, wherein the controller sets at least one of the plurality of bits to an error correction bit that indicates one of a first state and a second state; assigns the first state to the error correction bits that correspond to the data states having a minimum threshold level and a maximum threshold level and the second state to the error correction bits that correspond to the data state having other threshold level; and resets the error correction bit to the first state when the error correction bit indicates the second state.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application.