Abstract: A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.

Abstract: Embodiments of the present invention, which relate to the field of electronic technologies, provide a monitoring method, a monitoring apparatus, and an electronic device, which can accurately locate an error point in MPI information delivered by a system chip. The apparatus may include: an address filter, a read/write controller connected to the address filter, and a memory connected to the read/write controller, where the address filter is configured to acquire multiple pieces of MPI information, and obtain, by filtering the multiple pieces of MPI information, first MPI information corresponding to a first service that is preset; the read/write controller is configured to write, into the memory according to a time sequence of receiving the first MPI information, the first MPI information that is obtained by the address filter by filtering; and the memory is configured to store the first MPI information written by the read/write controller.

Abstract: Disclosed is an interface control circuit including an error detection unit, an error correction unit, and an adjustment control unit. The error detection unit is configured to detect whether an error occurs in error correction coded data transmitted via an interface. The error correction unit is configured to execute error correction processing of correcting the error when the error occurs. The adjustment control unit is configured to start adjustment processing of adjusting a transmission characteristic of the interface when the error occurs.

Abstract: A method of failure mapping is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes as a storage cluster. Each of the plurality of storage nodes has a non-volatile solid-state storage with flash memory or other types of non-volatile memory and the user data is accessible via the erasure coding from a remainder of the plurality of storage nodes in event of two of the plurality of storage nodes being unreachable. The method includes determining that a non-volatile memory block in the memory has a defect and generating a mask that indicates the non-volatile memory block and the defect. The method includes reading from the non-volatile memory block with application of the mask, wherein the reading and the application of the mask are performed by the non-volatile solid-state storage.

Abstract: Provided are a flash memory device, a flash memory system, and methods of operating the same. A method of operating a flash memory system includes selecting memory cells of a flash memory in response to an authentication challenge, programming pieces of input data into the selected memory cells, respectively, reading the selected memory cells and generating and storing control information, dividing the selected memory cells into at least one first region memory cell and at least one second region memory cell based on the control information, and setting read values of the at least one first region memory cell and the at least one second region memory cell as a first value and a second value, respectively, and generating an authentication response in the response to the authentication challenge.

Abstract: A control device for use in a broadcast system includes a broadcast controller that controls a broadcast transmitter of the broadcast system that broadcasts broadcast signals in a coverage area for reception by terminals including a broadcast receiver and a broadband receiver, and a broadband controller that controls a broadband server of a broadband system that provides redundancy data to terminals within the coverage area. The broadband controller is configured to control the provision of redundancy data by the broadband server for use by one or more terminals which use the redundancy data together with broadcast signals received via said broadcast system for recovering content received within the broadcast signals and/or provided via the broadband system.

Abstract: Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied.

Abstract: A method for error tracking a log subsystem of a file system is provided. The method includes: when a data block of the log subsystem is recovered to an original position in the file system, calculating a verification code of the data block to obtain a second verification code; determining whether a verification result between the second verification code and a first verification code of the data block stored in a spare space in a submit block of the log subsystem in a disk is consistent; and when the verification result is inconsistent, processing the data block corresponding to the inconsistent verification result. With the above method, given that system performance is least affected, an error and a position of the error of the log subsystem of the file system can be more accurately detected to enhance the reliability of the log subsystem.

Abstract: In one embodiment, a BIST (built-in self-test) engine performs BIST testing of embedded memory in an integrated circuit device (e.g., an FPGA) via an (e.g., hard-wired, dedicated, low-latency) bus from the configuration bitstream engine. During BIST testing, data is written into the embedded memory at-speed, which may require the bitstream engine to produce a higher frequency than originally used for configuration. Between consecutive write operations, the BIST engine is capable of reading the previously written set of data from the embedded memory and comparing that read-back data with the corresponding original set of data to determine whether a BIST error has occurred. By performing back-to-back write/read-back operations faster than the configuration speed and using a dedicated W/RB bus, BIST testing can be optimally performed without false-positive-invoking delays and undesirable resource utilization.

Abstract: A method for detecting a data bit inversion (DBI) error in a memory system is disclosed. The method and system comprise calculating an error correcting code (ECC) from each of the 8 beats of a burst of data such that no more than one bit per byte is included in each ECC calculation. The method and system further include determining if there is an inversion of one byte in the burst.

Abstract: A method of testing non-volatile memory arrays. A first test stage including at least a first stage read uses a first step size for setting current for BCC testing and/or voltage for VT testing for reading at least some memory cells. A second test stage including at least one second stage read uses an adjusted step size less in magnitude than the first step size for reading at least some memory cells. Provided no bit pattern match by the second test stage and/or the adjusted step size does not meet a predetermined minimum resolution (PMR), one or more additional test stages including additional array searching are added using a fixed step size less in magnitude than the adjusted step size including at least one read until a final read determines the predetermined repeating bit pattern is matched and a fixed step size for the final read meets the PMR.

Abstract: An encoding apparatus which performs encoding such as Low Density Parity Check (LDPC) encoding is provided. The encoding apparatus includes: an encoder encoding input bits using a parity check matrix including a plurality of blocks, each being formed of a first information word sub-matrix and a first parity sub-matrix arranged next to each other, and a second information sub-matrix and a second parity sub-matrix arranged next to each other; a bit determiner determining a value of a last sub-parity bit among sub-parity bits generated by encoding the input bits with respect to a first block among the plurality of blocks; and a bit modifier reversing values of bits generated by encoding the input bits with respect to a second block next to the first block based on the value of the last parity bit among the sub-parity bits generated by the encoding with respect to the first block.

Abstract: A method includes decoding, by a receiver device, a spread spectrum coded stream of information including a multiple codeword blocks. The decoding includes determining a number of invalid codewords in a particular block of codewords. Based on a first particular number of invalid codewords in the particular block of codewords, the particular block of codewords is demapped, and parity codewords of the particular block of codewords are discarded. Based on a second particular number of invalid codewords in the particular block of codewords, a subset of syndrome components is computed using one or more coding enumerations with an update procedure for the subset of syndrome components, if all of the subset components are zero an erroneous bit is found, otherwise coding enumerations continue, the particular block of codewords is demapped, and parity codewords of the particular block of codewords are discarded.

Abstract: Embodiments of decoders having early decoding termination detection are disclosed. The decoders can provide for flexible and scalable decoding and early termination detection, particularly when quasi-cyclic low-density parity-check code (QC-LDPC) decoding is used. In one embodiment, a decoder iteratively decodes a data unit using a decoding matrix comprising a plurality of layers. After at least one iteration of decoding the data unit, the decoder determines whether the decoded data unit from a completed iteration and one or more layers of the plurality of layers satisfy a parity check equation. In response to determining that the decoded data unit from the completed iteration and each layer of the plurality of layers satisfy the parity check equation, the decoder terminates decoding the data unit. Advantageously, the termination of decoding of the data unit can reduce a number of iterations performed to decode the data unit.

Abstract: The present invention is applicable to the field of error correction coding, and provides a circuit, an encoder and a method for parallel BCH coding. The method comprises: performing an XOR operation on input sequences {m(p?1), m(p?2), . . . , m(0)} in a current period in sequence corresponding to output upper bits of the previous period of a register separately, outputting operation results as selection signals to a selector, selecting P constant-multinomials {xr<<0) mod g(x), (xr<<1) mod g(x), . . . , (xr<<(p?1)) mod g(x)} with 0 separately in sequence, shifting the selection results and the output of the previous period of the register in P bits towards the upper bits and outputting the selection results, summing the selection results and outputting the sum to the register to serve as an output of the current period of the register; the above steps are repeated specific times to obtain final code output.

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform error correction code decoding on the memory units. The controller may be configured to generate a plurality of original log likelihood ratios each comprising a real value. The controller may be configured to convert each of the original log likelihood ratios to a converted log likelihood ratio comprising a fixed point value. The conversion comprises (a) scaling down a magnitude of each of the original log likelihood ratios, and (b) rounding each of the original log likelihood ratios having a scaled down magnitude to the fixed point value.

Abstract: In a network for reliable transfer of packets from a transmitter to a receiver using an Internet Protocol (IP), a system for packet recovery comprising a detection block (detector) for packet loss detection and a probe device (probe) for Forward Error Correction (FEC) packets transmission, wherein the detector includes means for sending a missing packet report to the probe upon detecting a missing packet, wherein the probe includes means for storing received packets, sending FEC packets and adapting a size of the FEC packets to an error rate computed from the missing packet reports, wherein the size of FEC packets is made larger or smaller responsive to the error rate increasing or decreasing, respectively, and wherein the probe is located close to the transmitter for reliable packets reception and the detector is located close to the receiver for reliably detecting loss of packets in a receiver's surroundings.

Abstract: A method for transmitting data using a convolutional turbo code (CTC) encoder. Specifically, the method comprises: encoding input data bits, which have been input through two input ports of the CTC encoder; interleaving the input data bits using four CTC interleaver parameters P0, P1, P2 and P3 corresponding to sizes of the input data bits; encoding the interleaved data bits; and selectively transmitting the input data bits, the first encoded bits and the second encoded bits, in accordance with a predetermined coding rate. Here, P0 is a relative prime number to N, which is ½ of the size of each of the input data bits, P2 has a value of N?1, and an absolute value of a difference between P1 and P3 is 1.

Abstract: Embodiments relate to performing a memory scrubbing operation that includes injecting an error on a write operation associated with a memory address. One or more errors are detected during a two-pass scrub operation on the memory address. Based on a result of the two-pass scrub operation, one or more of a hard error counter associated with the memory address and a soft error counter associated with the memory address is selected. The one or more selected counters are updated based on the result of the two-pass scrub operation.

Abstract: A communication device for uplink transmission with a first type of information and a second type of information includes a demultiplexing circuit, a vector selection circuit, a permutation circuit and a Reed-Muller encoding circuit. The demultiplexing circuit generates a first group of information bits and a second group of information bits according to the first type of information and the second type of information. The vector selection circuit selects code vectors from a predetermined vector set for the first group of information bits and the second group of information bits. The permutation circuit permutes the code vectors according to the first group of information bits and according to the second group of information bits. The Reed-Muller encoding circuit encodes the first group of information bits and the second group of information bits with the permuted code vectors for providing different levels of protection.