Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.

Abstract: A memory device includes a plurality of rows of memory cells, a refresh period determination unit, and a refresh control unit. The plurality of rows of memory cells includes a first row and one or more second rows. The refresh period determination unit is configured to set a refresh period according to read data from the first row. A refresh control unit is configured to control refreshing the one or more second rows based on the refresh period and to control obtaining the read data from the first row based on an adjustment interval.

Abstract: Indirect testing of multiple I/O interface signal lines concurrently. A system distributes a test data sequence to a group of signal lines. Each signal line receives the test data sequence and checks for errors in receiving the test data sequence at an associated I/O buffer. The system includes an error detection mechanism for each signal line. The system also includes an error detection mechanism for the group of multiple signal lines. If the I/O buffer receives any bit of the test data sequence incorrectly, the signal line error detection indicates an error. The group error detection accumulates pass/fail information for all signal lines in the group. Rather than sending a pass/fail indication on every cycle of the test, the group error detection can count pass/fail information for all signal lines of the group for all bits of the test data sequence and indicate error results after the entire test data is received.

Abstract: Methods and apparatus are provided for encoding and decoding via authenticated error correcting codes, such as secure LT codes, secure Raptor codes, block codes and/or rateless codes. Encoded symbols are generated via an authenticated error correcting code by applying a Luby Transform (LT) code to a plurality of message symbols to produce one or more intermediate symbols using a pseudo random number generator (PRNG) to select the plurality of message symbols to combine to produce the intermediate symbols; encrypting the intermediate symbols to produce encrypted symbols; computing an authentication value, such as a message authentication code (MAC), over one or more of the one or more encrypted symbols; and appending the authentication value to the corresponding encrypted symbols to form the encoded symbols. Block scalable and random scalable constructions are also provided, as well as decoding techniques for all of the constructions.

Abstract: A method for processing a plurality of received copies of the same original data, the method comprising performing maximum ratio combining on equivalent data portions of the received copies to derive at least one further equivalent data portion. The received and the constructed copies are then divided into sub-portions and combinations of divided sub-portions are assembled to provide reconstructed data portions. An error rate assessment is performed on the reconstructed data portions; and on this basis one is selected as an output.

Abstract: Embodiments relate to performing a memory scrubbing operation that includes injecting an error on a write operation associated with a memory address. One or more errors are detected during a two-pass scrub operation on the memory address. Based on a result of the two-pass scrub operation, one or more of a hard error counter associated with the memory address and a soft error counter associated with the memory address is selected. The one or more selected counters are updated based on the result of the two-pass scrub operation.

Abstract: A low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages, a check node processor operable to generate the check node to variable node message vectors and to calculate checksums based on the variable node to check node messages, and a convergence detector and bit map generator operable to convergence of the perceived values and to generate at least one bit map that identifies variable nodes that are connected to check nodes with unsatisfied parity checks.

Abstract: The various implementations described herein include systems, methods and/or devices that may enhance the reliability with which data can be stored in and read from a memory. The method includes, in response to one or more host read commands, reading data from a set of memory cells in a flash memory array in accordance with a first reading threshold voltage and performing an error correction process on the read data to produce error correction information. The method further includes determining, based on the error correction information, whether to adjust the first reading threshold voltage, and upon determining to adjust the first reading threshold voltage, setting the value of the first reading threshold voltage to a value greater or less than a current value of the first reading threshold voltage. In some implementations, the method further includes initiating a recalibration of the first reading threshold voltage when a predefined condition occurs.

Abstract: A transmitter for broadcasting data in a broadcasting system that improves the decoding quality, if needed, comprises a data input, and an encoder for error correction code encoding the input data words into codewords, a codeword comprising a basic codeword portion and an auxiliary codeword portion, wherein said encoder is adapted for generating said basic codeword portion from an input data word according to a first code and for generating said auxiliary codeword portion from an input data word according to a second code, said basic codeword portion being provided for regular decoding and said auxiliary codeword portion being provided as incremental redundancy if regular decoding of the codeword by use of the basic codeword portion is erroneous. Further, the transmitter comprises a data mapper for mapping the codewords onto frames of a transmitter output data stream, and a transmitter unit for transmitting said transmitter output data stream.

Abstract: A correctable parity-protected memory system may include a parity-protected memory configured to hold dirty data, an error correction register configured to hold data, an exclusive-OR (XOR) circuit configured to exclusive-OR dirty data that is written into and removed from the parity-protected memory with the data in the error-correction register, and a controller. The controller may be configured to cause the results of the XOR circuit to accumulate in the error-correction register each time dirty data is written into and removed from the parity-protected memory, and, in response to detection of a fault in dirty data in the parity-protected memory, correct the fault based on the data in the error-correction register and dirty data in the parity-protected memory.

Abstract: A system for improving the management and usage of blocks based on intrinsic endurance may be used to improve memory usage for flash memory, such as a memory card. The overall card endurance may be extended by cycling blocks with higher intrinsic endurance over the lowest endurance target of the worst block. This may be accomplished by managing blocks with different intrinsic endurance values internally or by partitioning the blocks with different intrinsic endurance values externally for different usage.

Abstract: A method of managing cache memory includes accessing a cache memory at a primary index that corresponds to an address specified in an access request. A determination is made that accessing the cache memory at the primary index does not result in a cache hit on a cache line with an error-free status. In response to this determination, the primary index is mapped to a secondary index and data for the address is written to a cache line at the secondary index.

Abstract: An apparatus includes an error correction code circuit and an error correction code selection circuit. The error correction code circuit may be configured to encode and decode data using any of a plurality of error correction codes. The error correction code selection circuit may be configured to control which of the plurality of error correction codes is used by the error correction code circuit to encode and decode data responsive to one or more reliability statistics and predetermined data characterizing distribution properties of each of the plurality of error correction codes.

Abstract: Technologies are described herein for recovering data in a storage device comprising a controller and a plurality of storage units. The controller receives a data stream, and divides the data stream into a plurality of data blocks, obtains a code block using the plurality of data blocks. When there is one or more blocks with damaged data in the plurality of data blocks and the code block, the controller obtains a sub-block from the Mth bit to the Nth bit of each block in the plurality of data blocks and the code block as a set, and reconstructs data in one or more sub-blocks with damaged data using other sub-blocks with undamaged data in the set.

Abstract: A scan test circuit includes: a pulse generator, for generating differential pulses according to a system clock signal; a functional path, including: a D-type latch clocked by the differential pulses; a test path, including: a scan latch clocked by a test clock signal; and a tri-state inverter. When a test enable signal is enabled, the generation of the differential pulses is disabled.

Abstract: A method for applying a sequence of sensing/read reference voltages in a read channel includes (A) setting a read window based on an estimate of a read channel, (B) setting first, second, and third values of a sequence of sensing voltages to values corresponding to different ones of (i) a left-hand limit of the read window, (ii) a right-hand limit of the read window, and (iii) a point central to the read window, (C) determining whether first, second and third reads are successful, and (D) if the first, second and third reads are not successful, setting fourth and fifth values of the sequence of sensing voltages to values corresponding to different ones of (i) a point between the left-hand limit and the point central to the read window and (ii) a point between the right-hand limit and the point central to the read window.

Abstract: The present invention provides a data storage device including a flash memory and a controller. The controller is configured to perform a first read operation to read a first page corresponding to a first word line of the flash memory according to a read command of a host, and perform a distribution-adjustment procedure when data read by the first read operation cannot be recovered by coding, wherein the controller is further configured to perform an adjustable read operation to read a second page corresponding to a second word line of the flash memory in the distribution-adjustment procedure.

Abstract: A circuitry for error correction includes a plurality of subcircuits for determining intermediate values Zw0, Zw1, Zw2, Zw3 to be used as coefficients in an error correction expression (z1i, z2i, . . . , zmi)=Zw3·?3ji+Zw2·?2ji+Zw1·?ji+Zw0. The intermediate values Zw0, Zw1, Zw2, Zw3 are determined depending on subsyndromes s1, s3, s5 so that in case of a 1-bit, 2-bit, or 3-bit error zi=(z1i, z2i, . . . , zmi)=(0, 0, . . . , 0) when an error occurred in the bit position i, and zi=(z1i, z2i, . . . , zmi)?(0, 0, . . . , 0) when no error occurred in the bit position i. A correction value ?vi= for the bit position i may then be determined on the basis of the error correction expression evaluated for ?ji.

Abstract: A method for reconstructing a physically uncloneable function (PUF) A for use in an electronic device is provided. The method includes generating a potentially erroneous PUF At and performing a preliminary correction of the potentially erroneous PUF At by means of a stored correction vector Deltat-1, to obtain a preliminarily corrected PUF Bt. The PUF A is reconstructed from the preliminarily corrected PUF Bt by means of an error correction algorithm. A corresponding apparatus is also provided.

Abstract: The present invention is related to systems and methods for serial application of different decode algorithms to a processing data set. In some cases, a first data decode algorithm may be applied to a first detected output, and a second data decode algorithm may be applied to a second detected output. In such a case, the second detected output may be generated based at least in part on the result of applying the first data decode algorithm.