Patents Examined by Christine Enad
-
Patent number: 11670719Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including a first semiconductor pattern on a substrate, the first semiconductor pattern including a lower channel; a second semiconductor pattern on the first semiconductor pattern and spaced apart from the first semiconductor pattern in a vertical direction, the second semiconductor pattern including an upper channel extending in the vertical direction; a gate electrode covering the lower channel and surrounding the upper channel; and source/drain patterns on opposite sides of the upper channel, wherein the substrate and the first semiconductor pattern have a doping concentration of 1019/cm3 or less.Type: GrantFiled: December 18, 2020Date of Patent: June 6, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Sungmin Kim
-
Patent number: 11658216Abstract: A method includes depositing a gate dielectric layer; depositing a work-function (WF) metal layer over the gate dielectric layer; and etching the WF metal layer through an etch mask, thereby removing the first portion of the WF metal layer while keeping the second portion of the WF metal layer, wherein a sidewall of the second portion of the WF metal layer is exposed. The method further includes forming a first barrier on the sidewall of the second portion of the WF metal layer and depositing a gate metal layer. A first portion of the gate metal layer is deposited over the gate dielectric layer, a second portion of the gate metal layer is deposited over the first barrier and the second portion of the WF metal layer. The first barrier is disposed between the first portion of the gate metal layer and the second portion of the WF metal layer.Type: GrantFiled: April 16, 2021Date of Patent: May 23, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shahaji B. More, Chandrashekhar Prakash Savant
-
Patent number: 11653545Abstract: A transparent display device for providing only a viewer located at the front with an image is disclosed. The transparent display device comprises a substrate provided with a first subpixel, a second subpixel and a third subpixel, a first electrode provided in each of the first subpixel, the second subpixel and the third subpixel on the substrate, a light emitting layer provided on the first electrode, a second electrode provided on the light emitting layer, an upper color filter provided over the second electrode, a lower color conversion layer provided between the substrate and the first electrode, and a lower color filter provided between the substrate and the lower color conversion layer.Type: GrantFiled: February 24, 2022Date of Patent: May 16, 2023Assignee: LG Display Co., Ltd.Inventors: Jiho Ryu, Taehan Park, Dongyoung Kim
-
Patent number: 11652041Abstract: A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A second distance is present between a second gate of the gates and the first conductive segment. The first distance is greater than the second distance.Type: GrantFiled: July 16, 2021Date of Patent: May 16, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien, Pin-Dai Sue
-
Patent number: 11652159Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a fin layer. Dummy gates are formed over the fin layer, where the dummy gates are formed to taper from a smaller width at a top region of the dummy gates to a larger width at a bottom region of the dummy gates. Sidewall spacers are formed on sidewalls of the dummy gates. An interlayer dielectric is formed in regions between the dummy gates and contacts the sidewall spacers. The dummy gates are removed to form openings in the interlayer dielectric and to expose the sidewall spacers on sides of the openings in the interlayer dielectric. The sidewall spacers are etched at a greater rate at a top region of the sidewall spacers than at a bottom region of the sidewall spacers.Type: GrantFiled: October 27, 2020Date of Patent: May 16, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Shih-Yao Lin, Chih-Han Lin, Hsiao Wen Lee
-
Patent number: 11646361Abstract: A structure includes a semiconductor fin on a substrate. A first fin transistor (finFET) is on the substrate, and a second finFET is on the substrate adjacent the first finFET. The first finFET and the second finFET include respective pairs of source/drain regions with each including a first dopant of a first polarity. An electrical isolation structure is in the semiconductor fin between one of the source/drain regions of the first finFET and one of the source/drain regions for the second FinFET, the electrical isolation structure including a second dopant of an opposing, second polarity. The electrical isolation structure extends to an upper surface of the semiconductor fin. A related method is also disclosed.Type: GrantFiled: March 4, 2021Date of Patent: May 9, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Arkadiusz Malinowski, Alexander M. Derrickson, Haiting Wang
-
Patent number: 11646315Abstract: Semiconductor structures and fabrication methods thereof are provided. The semiconductor includes a substrate; a gate structure on the substrate; and a dielectric layer on the substrate and covering sidewall surfaces of the gate structure. The dielectric layer includes an opening passing through the gate structure along a direction perpendicular to an extending direction of the gate structure. The semiconductor structure also includes a first isolation layer in the opening and with a top surface lower than a top surface of the gate structure.Type: GrantFiled: May 17, 2021Date of Patent: May 9, 2023Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Shuaijie Chi, Haiyang Zhang, Ermin Chong, Wei Tian
-
Patent number: 11646358Abstract: A method is presented for forming a self-aligned middle-of-the-line (MOL) contact. The method includes forming a fin structure over a substrate, depositing and etching a first set of dielectric layers over the fin structure, etching the fin structure to form a sacrificial fin and a plurality of active fins, depositing a work function metal layer over the plurality of active fins, depositing an inter-layer dielectric (ILD) and a second set of dielectric layers. The method further includes etching the second set of dielectric layers and the ILD to form a first, via portion and to expose a top surface of the sacrificial fin, removing the sacrificial fin to form a second via portion, and filling the first and second via portions with a conductive material to form the MOL contact in the first via portion and a contact landing in the second via portion.Type: GrantFiled: April 25, 2022Date of Patent: May 9, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yann Mignot, Indira Seshadri, Su Chen Fan, Christopher J. Waskiewicz, Eric Miller
-
Patent number: 11637090Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.Type: GrantFiled: July 30, 2021Date of Patent: April 25, 2023Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya, Ramamoorthy Ramesh
-
Patent number: 11621378Abstract: An optoelectronic component includes an optoelectronic semiconductor chip that, during intended operation, generates primary radiation coupled out of the semiconductor chip via an emission side of the semiconductor chip; and a first conversion element on the emission side, wherein the first conversion element includes a first matrix material and first phosphor particles in the form of quantum dots, the first phosphor particles are distributed and embedded in the first matrix material, and the first matrix material is formed by a polysiloxane in which an atomic percentage of carbon is smaller than an atomic percentage of oxygen.Type: GrantFiled: March 18, 2019Date of Patent: April 4, 2023Assignee: OSRAM OLED GmbHInventors: Dajana Durach, Kathy Schmidtke
-
Patent number: 11621249Abstract: A 3D semiconductor device, the device including: a first level; and a second level, where the first level includes single crystal silicon and a plurality of logic circuits, where the second level is disposed above the first level and includes a plurality of arrays of memory cells, where the single crystal silicon includes an area, and where the area is greater than 1,000 mm2.Type: GrantFiled: August 6, 2021Date of Patent: April 4, 2023Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
-
Patent number: 11616129Abstract: Patterning methods for forming patterned device substrates are provided. Also provided are devices made using the methods. The methods utilize photoresist features have re-entrant profiles to form a secondary metal hard mask that can be used to pattern an underlying device substrate.Type: GrantFiled: December 16, 2020Date of Patent: March 28, 2023Assignee: Wisconsin Alumni Research FoundationInventors: Zhenqiang Ma, Yei Hwan Jung
-
Patent number: 11610818Abstract: A semiconductor structure includes a first metal gate structure and a second metal gate structure. The first metal gate structure includes a first high-k gate dielectric layer, a first work function metal layer over the first high-k gate dielectric layer, and a first intervening layer between the first high-k gate dielectric layer and the first work function metal layer. The second metal gate structure includes a second high-k gate dielectric layer and a second work function metal layer over the second high-k gate dielectric layer. The first work function metal layer and the second work function metal layer include a same material. A thickness of the first work function metal layer is less than a thickness of the second work function metal layer.Type: GrantFiled: January 28, 2021Date of Patent: March 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventor: Chien-Hao Chen
-
Patent number: 11605566Abstract: A method of manufacturing a semiconductor device having metal gates and the semiconductor device are disclosed. The method comprises providing a first sacrificial gate associated with a first conductive type transistor and a second sacrificial gate associated with a second conductive type transistor disposed over the substrate, wherein the first conductive type and the second conductive type are complementary; replacing the first sacrificial gate with a first metal gate structure; forming a patterned dielectric layer and/or a patterned photoresist layer to cover the first metal gate structure; and replacing the second sacrificial gate with a second metal gate structure. The method can improve gate height uniformity during twice metal gate chemical mechanical polish processes.Type: GrantFiled: January 19, 2021Date of Patent: March 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tung-Huang Chen, Yen-Yu Chen, Po-An Chen, Soon-Kang Huang
-
Patent number: 11600532Abstract: A method for fabricating an integrated structure, using a fabrication system having a CMOS line and a photonics line, includes the steps of: in the photonics line, fabricating a first photonics component in a silicon wafer; transferring the wafer from the photonics line to the CMOS line; and in the CMOS line, fabricating a CMOS component in the silicon wafer. Additionally, a monolithic integrated structure includes a silicon wafer with a waveguide and a CMOS component formed therein, wherein the waveguide structure includes a ridge extending away from the upper surface of the silicon wafer. A monolithic integrated structure is also provided which has a photonics component and a CMOS component formed therein, the photonics component including a waveguide having a width of 0.5 ?m to 13 ?m.Type: GrantFiled: May 19, 2021Date of Patent: March 7, 2023Assignee: Rockley Photonics LimitedInventors: Aaron Zilkie, Andrew Rickman, Damiana Lerose
-
Patent number: 11600678Abstract: An organic light-emitting display device comprises a first thin-film transistor disposed on a substrate; and a second thin-film transistor disposed on the substrate and spaced apart from the first thin-film transistor. The first thin-film transistor comprises a first semiconductor layer, a first conductive layer disposed on the first semiconductor layer and that overlaps the first semiconductor layer, and a first insulating layer disposed between the first semiconductor layer and the first conductive layer. The second thin-film transistor comprises a second semiconductor layer, and a second conductive layer disposed on the second semiconductor layer and that overlaps the second semiconductor layer.Type: GrantFiled: May 4, 2021Date of Patent: March 7, 2023Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Woo Ho Jeong, Se Myung Kwon, Yoon Ho Kim, Seok Je Seong, Joon Hoo Choi
-
Patent number: 11594446Abstract: A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si1-xGex, Si1-xCx, Si1-x-yGexSny, Si1-x-y-zGexSnyCz, Ge1-xSnx, group IIIA-nitrides, semiconductor oxides, and any combination thereof.Type: GrantFiled: June 28, 2021Date of Patent: February 28, 2023Assignee: GlobalWafers Co., Ltd.Inventors: Igor Peidous, Srikanth Kommu, Gang Wang, Shawn George Thomas
-
Patent number: 11588052Abstract: Sub-fin isolation schemes for gate-all-around (GAA) transistor devices are provided herein. In some cases, the sub-fin isolation schemes include forming one or more dielectric layers between each of the source/drain regions and the substrate. In some such cases, the one or more dielectric layers include material native to the gate sidewall spacers, for example, or other dielectric material. In other cases, the sub-fin isolation schemes include substrate modification that results in oppositely-type doped semiconductor material under each of the source/drain regions and in the sub-fin. The oppositely-type doped semiconductor material results in the interface between that material and each of the source/drain regions being a p-n or n-p junction to block the flow of carriers through the sub-fin. The various sub-fin isolation schemes described herein enable better short channel characteristics for GAA transistors (e.g.Type: GrantFiled: August 6, 2018Date of Patent: February 21, 2023Assignee: Intel CorporationInventors: Biswajeet Guha, William Hsu, Tahir Ghani
-
Patent number: 11588041Abstract: A method for manufacturing a semiconductor device includes forming a gate trench over a semiconductor fin, the gate trench including an upper portion and a lower portion. The method includes sequentially forming one or more work function layers, a capping layer, and a glue layer over the gate trench. The glue layer includes a first sub-layer and a second sub-layer that have respective different etching rates with respect to an etching solution. The method includes removing the second sub-layer while leaving a first portion of the first sub-layer filled in the lower portion of the gate trench.Type: GrantFiled: October 14, 2020Date of Patent: February 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Jian-Jou Lian, Tzu Ang Chiang, Ming-Hsi Yeh, Chun-Neng Lin, Po-Yuan Wang, Chieh-Wei Chen
-
Patent number: 11581224Abstract: A method of forming a semiconductor transistor device. The method comprises forming a fin-shaped channel structure over a substrate and forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite endings of the fin structure. The method further comprises forming a metal gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain epitaxial structure and the second source/drain epitaxial structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.Type: GrantFiled: October 12, 2020Date of Patent: February 14, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang, Zhi-Chang Lin, Li-Zhen Yu