Abstract: Systems and methods for translation and transmission of video and audio data over a first-in-first-out interface (FIFO) in a field programmable gate array (FPGA) are provided. The method includes receiving audio and video data including a number of video frames, each with a plurality of video lines separated by a line blanking interval. A first video line is translated and transmitted to a packet-based network through the FIFO in the FPGA while concurrently buffering the audio data in an audio buffer in the FPGA. Next, at least a portion of the audio data in the audio buffer is transmitted to the packet-based network through the FIFO during the line blanking interval separating the first video line from a second video line. Where video frames are separated by frame blanking intervals the method further includes transmitting through the FIFO any data remaining in the buffer after the preceding line blanking interval.

Abstract: A storage enclosure connected to a server via an external network and includes a network switch, an expander that is connected to the network switch and that is configured to generate enclosure data that supports a format conforming with SCSI Enclosure Services, and a board management controller (BMC) that is connected to the network switch and the expander. The BMC is configured to translate the enclosure data into enclosure translating data that supports a Redfish® format. The expander is configured to, after generating the enclosure data, transmit the enclosure data through the network switch to the BMC via an internal network. The BMC is configured to translate the enclosure data into the enclosure translating data, and to transmit the enclosure translating data to the network switch. The network switch transmits the enclosure translating data to the server through the external network.

Abstract: A multi-processor device is disclosed. The multi-processor device includes interface circuitry to receive requests from at least one host device. A primary processor is coupled to the interface circuitry to process the requests in the absence of a failure event associated with the primary processor. A secondary processor processes operations on behalf of the primary processor and selectively receives the requests from the interface circuitry based on detection of the failure event associated with the primary processor.

Abstract: A system-on-chip including: a first slave having a first safety level; a second slave having a second safety level; a first master having a third safety level, the first master outputs a first access request for the first slave and a second access request for the second slave; a safety function protection controller that outputs first attribute information corresponding to the first safety level, second attribute information corresponding to the second safety level, and third attribute information corresponding to the third safety level; and an interconnect bus that receives the first, second and third attribute information, transfers the first access request to the first slave when it is determined that the third safety level is higher than or equal to the first safety level, and blocks the second access request when it is determined that the third safety level is lower than the second safety level.

Abstract: Multiple device stacks are interconnected in a ring topology. The inter-device stack communication may utilize a handshake protocol. This ring topology may include the host so that the host may initialize and load the device stacks with data and/or commands (e.g., software, algorithms, etc.). The inter-device stack interconnections may also be configured to include/remove the host and/or to implement varying numbers of separate ring topologies. By configuring the system with more than one ring topology, and assigning different problems to different rings, multiple, possibly unrelated, machine learning tasks may be performed in parallel by the device stack system.

Abstract: The present application discloses a computing system and an associated method. The computing system includes a first host, a second host, a first memory extension device and a second memory extension device. The first host includes a first memory, and the second host includes a second memory. The first host has a plurality of first memory addresses corresponding to a plurality of memory spaces of the first memory, and a plurality of second memory addresses corresponding to a plurality of memory spaces of the second memory. The first memory extension device is coupled to the first host. The second memory extension device is coupled to the second host and the first memory extension device. The first host accesses the plurality of memory spaces of the second memory through the first memory extension device and the second memory extension device.

Abstract: Computing apparatus includes a central processing unit (CPU) and a root complex connected to the CPU and to a first peripheral component bus, which has at least a first downstream port for connection to at least one peripheral device. Switching logic has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, and is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in an address space of the second peripheral component bus.

Abstract: A server rack has server sleds, each including a motherboard upon which is mounted: a memory module, a cache, at least one CPU connected to the cache, a memory controller connected to the cache and the memory module, an I/O hub, and a fabric interface (FIC) having a memory bridge and optical transceivers, where this memory bridge is connected to the I/O hub through this motherboard. The rack also has a memory sled disaggregated from the server sleds and that includes: a motherboard upon which is mounted: memory modules and a FIC having a memory bridge, a memory controller and optical transceivers, wherein this memory controller is connected to these memory modules through this motherboard, and wherein this memory bridge connects the memory controller to the optical transceivers. The rack has a photonic cross-connect switch interconnected by optical fiber cables to the optical transceivers of the server and memory sleds.

Abstract: An interface for coupling an agent to a fabric supports a set of coherent interconnect protocols and includes a global channel to communicate control signals to support the interface, a request channel to communicate messages associated with requests to other agents on the fabric, a response channel to communicate responses to other agents on the fabric, and a data channel to couple to communicate messages associated with data transfers to other agents on the fabric, where the data transfers include payload data.

Abstract: A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data burst to be initiated by toggling a logical level of a control pin from a first level corresponding to a data burst inactive mode to a second level corresponding to a data burst active mode, wherein the data burst corresponds to a data transfer across an interface bus, causing the data burst to be suspended by toggling the logical level of the control pin from the second level to a third level corresponding to a data burst suspend mode, and causing the data burst to be resumed by toggling the logical level of the control pin from the third level to the second level.

Abstract: Systems and methods for unifying multiple audio bus interfaces in an audio system are disclosed herein. In one aspect, an integrated circuit (IC) comprises a primary slave audio device comprising a first control circuit, and a dependent slave audio device comprising a second control circuit. The primary slave audio device and the dependent slave audio device are communicatively coupled via a slave status link, and the first control circuit and the second control circuit each configured to receive, from a master audio device, a mode instruction that indicates operation in one of a detach mode and a unify mode. The second control circuit is configured to, while operating in the detach mode, transmit a slave status to the master audio device via a second control lane, and, while operating in the unify mode, transmit the slave status to the primary slave audio device via the slave status link.

Abstract: An electronic device is provided. The electronic device includes a first power management integrated circuit (PMIC) with a first fault controller connected to a first node and a first interface circuit connected to a second node; a second PMIC with a second fault controller connected to the first node and a second interface circuit connected to the second node; and a third PMIC with a third fault controller connected to the first node and a third interface circuit connected to the second node. The first fault controller is configured to, during a power on sequence or a power off sequence, detect a change in a voltage level of the first node. The first interface circuit is configured to communicate with any one or any combination of the second interface circuit and communication and the third interface circuit based on the change in the voltage level of the first node.

Abstract: An equalization training method and apparatus are described. The method includes obtaining a training rate of each of a master chip and a slave chip in a target phase of equalization training. The method also includes determining a target rate threshold interval within which the training rate in the target phase falls, determining, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configuring the target equalization timeout period as an equalization timeout period in the target phase.

Abstract: In a system and method of operating a system that includes a controller and a first bus participant and a successor, the bus participant and successor each has a circuit arrangement arranged between an output and an input, a first resistor is arranged between the output and the supply voltage terminal, a second resistor is arranged between the input and a ground terminal, a third resistor can be arranged between the input and the supply voltage terminal by a first controllable semiconductor switch, and a fourth resistor can be arranged between the output and the supply voltage terminal by a second controllable semiconductor switch.

Abstract: A computer-readable medium may store machine-readable instructions for execution by a processor. There may be a connection between the processor and a virtual computer. The processor may establish a first data channel between the processor and the virtual computer based on the connection between the processor and the virtual computer. The connection may comprise a second data channel to transfer input/output (I/O) data between the processor and the virtual computer. The processor may receive an output message from the virtual computer via the first data channel. The processor may identify an I/O device coupled to the processor based on the output message. The processor may provide an output signal to the I/O device, the output signal based on the output message.

Abstract: A distributed computing system in an autonomous driving vehicle (ADV) includes a main compute system and multiple subsystems, and a bus structure that connect the main compute system and the multiple subsystems. The bus structure provides uniform system-to-system connectivity. A host field-programmable gate array (FPGA) agent coupled to the main compute system can communicate with slave FPGA agents on the subsystems via multiple pairs of bus interface protocols of a particular type. The bus interfaces on the FPGA agents supports the uniform system-to-system connectivity.

Abstract: Techniques provide communications bandwidth between storage processors (SPs). Such techniques involve electrically coupling the SPs with a first side of a midplane. Such techniques further involve electrically coupling a network interface controller (NIC) device with a second side of the midplane that is opposite the first side of the midplane. Such techniques further involve configuring the NIC device to convey communications between the SPs while the SPs are electrically coupled with the first side of the midplane and while the NIC device is electrically coupled with the second side of the midplane that is opposite the first side of the midplane.

Abstract: Various embodiments include systems and methods pertaining to a network sensor host configured to implement a receive side scaling (RSS) configuration component in a security environment. The RSS configuration component may be used to automatically generate an RSS configuration comprising one or more settings customized for the network sensor host based at least in part on hardware information of the network sensor host. In some embodiments, the RSS configuration may be applied to change settings of a network interface driver of the network sensor host, e.g., to implement RSS and multithreading for network sensor tasks.

Abstract: In some examples, a method includes receiving a transaction at an inbound port, the transaction including a requester identification (ID), a traffic class, and a peripheral component interconnect express (PCIe) address. The method includes providing an attribute based at least in part on the traffic class. The method includes providing a context ID based on the attribute and the requester ID. The method includes accessing a region of memory responsive to the transaction, the region of memory corresponding to the context ID.

Abstract: A vehicle control system is communicably connected with an electronic controller and a control circuit. The control circuit is controlled by the electronic controller as a control target. The vehicle control system communicates with the electronic controller using a control communication frame and communicates with the control circuit using a circuit communication frame. The control communication frame and the circuit communication frame have different formats from one another. The vehicle control system includes at least one of a first sequence circuit converting the control communication frame into the circuit communication frame or a second sequence circuit converting the circuit communication frame into the control communication frame.