Patents Examined by Christopher A Daley
  • Patent number: 11169569
    Abstract: The disclosure provides a USB expanding device comprising a plurality of USB type-C connection units, a transmission controller, and a main controller. Each of a USB type-C connection unit includes a USB type-C port, a multiplexer, and a power transmission controller. The USB type-C port provides for connecting to an external device. The multiplexer connects to the USB type-C port and the power transmission controller. The transmission controller connects to the multiplexers of each of the USB type-C connection units for controlling the transmission of data, and the main controller connects to the power transmission controllers of each of the USB type-C connection units to distribute power according to the charging request information of the power transmission controllers.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: November 9, 2021
    Assignee: ASUSTEK COMPUTER INC.
    Inventor: Jian-Hui Lee
  • Patent number: 11171805
    Abstract: Generating a CAN ID represented by a predetermined bit used in CAN communication, including a first bit allocation process for allocating N-th to M-th bits of the CAN ID for use classification, a second bit allocation process for allocating O-th to P-th bits of the CAN ID for target classification, and a third bit allocation process for allocating Q-th to R-th bits of the CAN ID for data number classification (N, M, O, P, Q and R are integers and satisfy a relation of R>Q, P>O, M>N, N>P, O>R).
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: November 9, 2021
    Assignee: LG CHEM, LTD.
    Inventor: Mi So Park
  • Patent number: 11169947
    Abstract: A data transmission system includes a host, a universal serial bus (USB) interface adaptor, a first-in first-out (FIFO) interface adaptor, a plurality of functional circuits, and a bus bridge circuit. The host accesses data according to the communications protocols of USB. The USB interface adaptor accesses data through a first port according to the communications protocols of USB, and accesses data through a second port according to the communications protocols of FIFO. The FIFO interface adaptor accesses data through a third port coupled to the second port according to the communications protocols of FIFO, and accesses data through a fourth port according to the communications protocols of a specific type of bus. The bus bridge circuit transmits the data received from the fourth port to a functional circuit according to the communications protocols of the specific type of bus.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: November 9, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chen-Tung Lin, Yuefeng Chen
  • Patent number: 11169944
    Abstract: To perform communication more definitely and efficiently. Communication is performed by a master that is a communication device having a communication initiative and a slave that is a communication device that performs communication under control of the master. The master assigns a group address to an arbitrary slave of a plurality of slaves joining in a bus setting a plurality of arbitrary slaves to one group and setting the group to a destination, and when it is confirmed that at least one or more slaves exit from the bus of the slaves to which the group address is assigned, the group address assigned to the remaining slaves is reset. The present technology is, for example, applicable to a bus IF.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: November 9, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Hiroo Takahashi, Naohiro Koshisaka
  • Patent number: 11162991
    Abstract: An electronic device is provided including a connector comprising a plurality of terminals, the connector being configured to be connected with an external device; a circuit electrically connected to at least a subset of the plurality of terminals; and a processor electrically connected to the circuit, wherein the processor is configured to detect a connection of the external device through the connector, detect a first impedance of a first electrical path including a first terminal of the plurality of terminals, detect a second impedance of a second electrical path including a second terminal of the plurality of terminals, and determine a connection direction of the external device connected through the connector, based on the first impedance and the second impedance.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: November 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaehwan Lee, Hoyeong Lim, Kihyun Park, Gihoon Lee, Duhyun Kim, Yongseung Yi, Dongil Son
  • Patent number: 11163453
    Abstract: A memory device comprises a smart buffer, and a memory area divided into a first memory area and a second memory area, wherein the smart buffer comprises a priority setting unit configured to receive a sensing data and a corresponding weight from a controller, determine a priority of the sensing data based on the weight, and classify the sensing data as one of first priority sensing data and second priority sensing data, and a channel controller configured to allocate at least one channel selected from among a plurality of channels to a first channel group, allocate at least another channel selected from among the plurality of channels to a second channel group, assign the first channel group to process the first priority sensing data in relation to the first memory area, and assign the second channel group to process the second priority sensing data in relation to the second memory area, wherein a number of data input/output (I/O) pins connected to the first channel group is greater than a number of data I/O
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: November 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngmin Jo, Daeseok Byeon, Tongsung Kim
  • Patent number: 11163715
    Abstract: A coarse-grained reconfigurable array accelerator for solving partial differential equations for problems on a regular grid is provided. The regular grid comprises grid cells which are representative for a physical natural environment wherein a list of physical values is associated with each grid cell. The accelerator comprises configurable processing elements in an accelerator-internal grid connected by an accelerator-internal interconnect system and memory arrays comprising memory cells. The memory arrays are connected to the accelerator-internal interconnect system. Selected ones of the memory arrays are positioned within the accelerator corresponding to positions of the grid cells in the physical natural environment. Thereby, each group of the memory cells is adapted for storing the list of physical values of the corresponding grid cell of the physical natural environment.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ronald Peter Luijten, Gagandeep Singh, Joost VandeVondele
  • Patent number: 11163714
    Abstract: Embodiments of the present disclosure relate to a method, an apparatus, an electronic device and a computer readable storage medium for determining connection relationships among a plurality of chips. The method includes determining identity information of a plurality of chips managed by a host, the plurality of chips being connected by respective inter-chip communication interfaces for inter-chip communication. The method further includes allowing one or more of the plurality of chips to acquire identity information of other chips connected to the inter-chip communication interface of the one or more chips. The method further includes reading identity information of the other chips by means of a management interface of the one or more chips with regard to communicating with the host, so as to determine connection relationships among the plurality of chips.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: November 2, 2021
    Inventors: Xianglun Leng, Hefei Zhu, Qingshu Chen, Zhibiao Zhao, Xiaozhang Gong
  • Patent number: 11157425
    Abstract: A memory device provides a first memory area and a second memory area. A smart buffer includes; a priority setting unit receiving sensing data and a corresponding weight, determining a priority of the sensing data based on the corresponding weight, and classifying the sensing data as first priority sensing data or second priority sensing data based on the priority, and a channel controller allocating a channel to a first channel group, allocating another channel to a second channel group, assigning the first channel group to process the first priority sensing data in relation to the first memory area, and assigning the second channel group to process the second priority sensing data in relation to the second memory area.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: October 26, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngmin Jo, Daeseok Byeon, Tongsung Kim
  • Patent number: 11144484
    Abstract: A method and electronic device for communicating audio signals with an audio input/output device is provided. The electronic device includes a USB type connection port, an audio processor configured to support conversion between a digital signal and an analog signal, and at least one processor configured to detect a connection of a peripheral device via the connection port, identify a type of the peripheral device, establish a first signal path for communicating the digital signal with the peripheral device through a first pin and/or a second pin included in the connection port based on whether the peripheral device supports a first mode, or establish a second signal path for communicating the analog signal with the peripheral device through the first pin and/or the second pin included in the connection port based on whether the peripheral device supports a second mode and whether a predetermined condition is satisfied.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: October 12, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaecheon Jeong, Hyunku Park
  • Patent number: 11144482
    Abstract: Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing transceivers, receivers, and/or transmitters of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided via a plurality of transceivers of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: October 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Glen E. Hush, Richard C. Murphy, Honglin Sun
  • Patent number: 11121109
    Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 14, 2021
    Assignee: Intel Corporation
    Inventors: Md Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Patent number: 11119955
    Abstract: To perform communication more definitely and efficiently. In a case of transferring a communication initiative in accordance with a request by a secondary master, a master determines whether or not the secondary master that has performed the request has a group management capability. Then, when it is determined that the secondary master has no group management capability, the master instructs all communication devices connected to a bus to reset a group address, and when it is determined that the secondary master has the group management capability, the master transfers the communication initiative in a state in which the group address is set. The present technology is, for example, applicable to a bus IF.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: September 14, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Naohiro Koshisaka, Hiroo Takahashi
  • Patent number: 11119965
    Abstract: Examples described herein provide a computer-implemented method that includes initializing a storage area network. The method further includes managing, using a virtualized fabric controller, the storage area network.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: September 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen Robert Guendert, Michael James Becht, Pasquale A. Catalano, Christopher J Colonna
  • Patent number: 11119969
    Abstract: Provided is a communication system including: a first communication bus available for communication of at least a first communication scheme; a second communication bus available for both communication of the first communication scheme and communication of a second communication scheme having a lower processing load than the first communication scheme; a plurality of first communication devices connected to both the first communication bus and the second communication bus; a plurality of second communication devices, connected to the second communication bus, which perform communication through the second communication scheme using the second communication bus; and a processor that detects an abnormality of the first communication bus, wherein each of the plurality of first communication devices performs communication through the first communication scheme using the first communication bus in a case where the abnormality of the first communication bus is not detected by the processor, and performs communicati
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: September 14, 2021
    Assignee: HONDA MOTOR CO., LTD.
    Inventor: Kazuhiro Okajima
  • Patent number: 11113215
    Abstract: An electronic device which schedules a plurality of tasks, and an operating method thereof. The electronic device includes a processor and a memory operatively connected to the processor, and when being executed, the memory stores instructions that cause the processor to: detect occurrence of an interrupt requesting performance of a second task while performing a first task; obtain reference values according to a time of the first task, and reference values according to a time of the second task; schedule the first task and the second task based on a reference value of the first task and a reference value of the second task which correspond to a time at which the interrupt occurs; and process the first task and the second task based on a result of the scheduling. Other embodiments are possible.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: September 7, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngmin Oh, Kibeom Kim, Sangho Lee, Yeona Hong, Gajin Song
  • Patent number: 11113218
    Abstract: The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data. The protocol conversion unit generates the second data by converting the first data from the first protocol to the second protocol. The slave interface detects errors in the copy data based on the error detection code. The slave interface also generates the first verification data by performing a conversion from one of the first protocol or the second protocol to the other for one of the second data or copy data. In addition, the slave interface compares the second verification data with the first verification data, using the other of the second data or copy as the second verification data.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: September 7, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sho Yamanaka, Toshiyuki Hiraki
  • Patent number: 11112844
    Abstract: A Universal Serial Bus (USB) Type-C and power delivery port with scalable power architecture is disclosed. In one aspect, at least two circuits for a USB port are consolidated into a single integrated circuit (IC). At least one of the at least two circuits is part of a Type-C port controller (TCPC) group of circuits including sensors associated with detecting whether a voltage and current are present at pins of a USB receptacle. At least the other one of the at least two circuits is selected from a battery-related group of circuits including a battery charging circuit, an over-voltage protection circuit, and a conditioning circuit. The more circuitry integrated into the single IC the more readily scalable the end product is for a multi-port device. Additional circuitry such as a light emitting diode (LED) driver may also be included in the single IC.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: September 7, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Christian Gregory Sporck, Georgios Konstantinos Paparrizos, Chunping Song
  • Patent number: 11100012
    Abstract: A method of applying feedback control on peripheral units supplying energy to manufacturing units in a manufacturing facility uses a trained model, and includes: mapping supply relations between peripheral units and manufacturing units into a schema; establishing communications with sensors monitoring peripheral unit metrics indicative of energy transfer from the peripheral units to the manufacturing units; training the model based on the schema and training data gathered by communication with the sensors during a training period, the trained model predicting energy usage by the peripheral machines with a specified degree of accuracy; and during a control period following the training period, gathering further data from the sensors and minimizing energy usage by the peripheral units while supplying the total energy demanded by the manufacturing units by controlling at least one of the peripheral units based on an outcome of inputting the further data into the trained model.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: August 24, 2021
    Assignee: Ecoplant Technological Innovation LTD
    Inventors: Aviran Yaacov, Yaron Harel, Mordechai Yaakov
  • Patent number: 11093427
    Abstract: A switch fabric is disclosed that includes a serial communications interface and a parallel communications interface. The serial communications interface is configured for connecting a plurality of slave devices to a master device in parallel to transmit information between the plurality of slave devices and the master device, and the parallel communications interface is configured for separately connecting the plurality of slave devices to the master device to transmit information between the plurality of slave devices and the master device, and to transmit information between individual ones of the plurality of slave devices. The parallel communications interface may comprise a dedicated parallel communications channel for each one of the plurality of slave devices. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: August 17, 2021
    Assignee: Bedrock Automation Platforms Inc.
    Inventors: James G. Calvin, Albert Rooyakkers