Abstract: An integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface communicates an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. The interface clock signal is synchronous with a data signal received by one of the first IC chip and the second IC chip. The logic clock signal is asynchronous with the data signal.

Abstract: A host data processing system method, apparatus, and architecture are provided for sharing a PCIe EP device with one or more lendee data processing systems in a PCIe cluster by extracting an RID value from a received PCIe transaction message corresponding to a PCIe function at the PCIe endpoint device, and then processing the RID value to identify an interconnect target port value which corresponds to a first lendee data processing system which is sharing the PCIe endpoint device, and then routing the PCIe transaction message through an interconnect on the host data processing system using an interconnect target output port corresponding to the first interconnect target port value to deliver the PCIe transaction message to the first lendee data processing system.

Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.

Abstract: The present disclosure relates to a Controller Area Network (CAN) system including: a CAN device and a monitoring device. The CAN device includes a transmit data (TXD) interface, a transmitter, a CAN BUS interface, and a control unit. The control unit reads out an identifier from a TXD message and compares the identifier with a reference tag. The CAN device generates a CAN BUS signal based on the TXD message at the CAN BUS interface. The control unit, if the comparison indicates that the identifier does not correspond to the reference tag, invalidates a representation of the TXD message by the CAN BUS signal and temporarily prevents another CAN BUS signal from being generated by the CAN device at the CAN BUS interface. The monitoring device receives an instruction message over a CAN BUS network and, in response, tests for reachability other CAN devices on the CAN BUS network.

Abstract: A device includes a first interface unit connected to a first controller area network (CAN) bus, a second interface unit connected to a second CAN bus, and a control unit configured to identify, in a case where transmission of a CAN frame is started, a CAN bus detected to be in a dominant state first after end of arbitration from the first CAN bus or the second CAN bus, as a CAN bus to which a transmission source device of the CAN frame is connected.

Abstract: A system and method checks packetized data retrieved from a bus that is ordinarily considered reliable that was already error checked and/or corrected before being placed on the bus by applying a hash or checksum or other function to each packet to produce a packet checksum and then applying another function to the ordered packet checksums and comparing the result to one sent by the device that checked and/or corrected, and sent, the data packets.

Abstract: A deterministic apparatus comprising a deterministic near-compute memory communicatively coupled with and proximate to a deterministic processor. The deterministic near-compute memory comprises a plurality of data banks having a global memory address space, a control bus, a data input bus and a data output bus for each data bank. The deterministic processor is configured to initiate, via the control bus, retrieval of a set of data from the plurality of data banks. The retrieved set of data comprises at least one row of a selected one of the data banks passed via the data output bus onto a plurality of stream registers of the deterministic processor.

Abstract: A data cable and a charging device are provided. The data cable includes a type-A interface and a type-C interface. The type-A interface and the type-C interface each includes a VBUS pin, a CC pin, a D+ pin, a D? pin, and a GND pin. A circuit identification module is disposed in the data cable, and the circuit identification module includes a switch circuit, a filtering circuit, a voltage regulator circuit, and a comparator circuit. The switch circuit is connected to a CC pin of the type-C interface, an output end of the voltage regulator circuit, a CC pin of the type-A interface, and an output end of the comparator circuit. Under the control of the comparator circuit, the switch circuit connects the CC pin of the type-C interface to the CC pin of the type-A interface or the output end of the voltage regulator circuit.

Abstract: A method of scheduling input/output operations for a storage system including determining a deadline for a storage operation, wherein the deadline is dependent on an expected latency of the storage operation; adding the storage operation to a queue of storage operations; and reordering the queue dependent upon the deadline of the storage operation and one or more deadlines of one or more storage operations in the queue of storage operations.

Abstract: A computer system is provided. The computer system includes a hub board, a common bus, and a plurality of Sibling boards. The hub board has an I/O controller hub, which includes a main communication chipset. The plurality of Sibling boards is coupled to the hub board by the common bus. Each of the Sibling boards includes a memory and at least one CPU. The memory is operative to host a Sibling operating system. The CPU is coupled to the memory. The Southbridge type chipset which resides in the hub board is shared amongst the plurality of Sibling boards. At least one of the plurality of Sibling boards functions as a master processing unit of the system. Sibling boards offer processing flexibility through the means of how they are configured in the system.

Abstract: First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.

Abstract: This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

Abstract: Techniques in wavelet filtering for advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements comprising a portion of a neural network accelerator performs flow-based computations on wavelets of data. Each processing element comprises a compute element to execute programmed instructions using the data and a router to route the wavelets in accordance with virtual channel specifiers. Each processing element is enabled to perform local filtering of wavelets received at the processing element, selectively, conditionally, and/or optionally discarding zero or more of the received wavelets, thereby preventing further processing of the discarded wavelets. The wavelet filtering is performed by one or more configurable wavelet filters operable in various modes, such as counter, sparse, and range modes.

Abstract: The present invention relates to a CAN node being configured to predict, based on the at least one response message and a reference response, a fault of the CAN network and to determine a fault location of the predicted fault of the CAN network. The present disclosure also relates to a CAN system and a method for the CAN node.

Abstract: Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a memory chiplet is disclosed. The memory chiplet includes a D2D interface of a first type for coupling to a host IC chip via multiple lanes. The D2D interface includes multiple unit interface modules, each of the multiple unit interface modules corresponding to a first set of signal path resources of a lowest granularity provided by the multiple lanes. A memory port includes a memory physical interface of a first memory type for accessing memory storage of the first memory type. The memory physical interface of the first memory type includes a second set of signal path resources corresponding to multiple memory channels of the first memory type. Mapping circuitry maps the second set of signal path resources to the first set of signal path resources in a manner that utilizes all of the first signal path resources for an integer number of the multiple unit interface modules.

Abstract: Techniques in placement of compute and memory for accelerated deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements comprising a portion of a neural network accelerator performs flow-based computations on wavelets of data. Each processing element comprises a compute element to execute programmed instructions using the data and a router to route the wavelets. The routing is in accordance with virtual channel specifiers of the wavelets and controlled by routing configuration information of the router. A software stack determines placement of compute resources and memory resources based on a description of a neural network. The determined placement is used to configure the routers including usage of the respective colors. The determined placement is used to configure the compute elements including the respective programmed instructions each is configured to execute.

Abstract: Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a memory chiplet is disclosed. The memory chiplet includes at least one memory die of a first memory type. Memory control circuitry is coupled to the at least one memory die. An interface circuit is for coupling to a host IC chiplet. The interface circuit includes data input/output (I/O) circuitry for coupling to multiple data lanes. Link directional control circuitry selects, for a first memory transaction, a first subset of the multiple data lanes to transfer data between the memory chiplet and the host IC chiplet.

Abstract: Various examples are directed to systems and methods for requesting an atomic operation. A first hardware compute element may send a first request via a network structure, where the first request comprises an atomic opcode indicating an atomic operation to be performed by a second hardware compute element. The network structure may provide an address bus from the first hardware compute element for providing the atomic opcode to the second hardware compute element. The second hardware compute element may execute the atomic operation and send confirmation data indicating completion of the atomic operation. The network structure may provide a second bus from the second hardware compute element and the first hardware compute element. The second bus may be for providing the confirmation data from the second hardware compute element to the first hardware compute element.

Abstract: The implementation of the present disclosure provides a memory, an operation method thereof and a memory system. For example, the memory can include a first memory plane, a second memory plane, and a plane data bus connected to each of the first memory plane and the second memory plane. The plane data bus can be configured to receive input data. The first memory plane can be configured to store first data of the input data. The second memory plane can be configured to store second data of the input data. The second data can be configured to indicate whether the first data has been performed with an inversion operation prior to transmission.

Abstract: An apparatus includes an interrupt cache having cache storage configured to store a plurality of interrupts received from an interrupt source, the plurality of interrupts corresponding to a plurality of interrupt events configured for execution by the plurality of interrupt service routines and a cache manager component configured to generate an interrupt message for transmission to the processing unit, the interrupt message generated to include at least one interrupt of the plurality of interrupts from the cache storage.