Abstract: A server rack has server sleds, each including a motherboard upon which is mounted: a memory module, a cache, at least one CPU connected to the cache, a memory controller connected to the cache and the memory module, an I/O hub, and a fabric interface (FIC) having a memory bridge and optical transceivers, where this memory bridge is connected to the I/O hub through this motherboard. The rack also has a memory sled disaggregated from the server sleds and that includes: a motherboard upon which is mounted: memory modules and a FIC having a memory bridge, a memory controller and optical transceivers, wherein this memory controller is connected to these memory modules through this motherboard, and wherein this memory bridge connects the memory controller to the optical transceivers. The rack has a photonic cross-connect switch interconnected by optical fiber cables to the optical transceivers of the server and memory sleds.

Abstract: A method including creating a first bus guide and a second bus guide of a plurality of bus guides for an integrated circuit is disclosed. The method includes routing the first bus guide and the second bus guide through a plurality of layout blocks of the integrated circuit. The method includes annotating the first bus guide or the second bus guide to identify a plurality of areas for placing a plurality of repeaters within the first bus guide or the second bus guide. The method includes, based on the annotated first bus guide and the second bus guide, generating, by at least one processor, a plurality of guidance directories corresponding to a plurality of routes through the plurality of layout blocks for placing the plurality of repeaters at the plurality of layout blocks on the identified plurality of areas on the first bus guide or the second bus guide.

Abstract: A subscriber station for a serial bus system and a method for communicating in a serial bus system. The subscriber station includes a communication control device for controlling a communication of the subscriber station with at least one other subscriber station of the bus system, a transmitting/receiving device for receiving a transmission signal generated by a communication control device of a subscriber station of the bus system in a frame from a bus of the bus system and for generating a reception signal from the received frame, and a connection quality block for detecting and evaluating a quality of a communication connection to a subscriber station of the bus system from the reception signal generated by the transmitting/receiving device by using at least two time quanta, into which the bit time of a bit of the generated reception signal is subdivided.

Abstract: A processing device to perform operations including detecting a first host system connected to a first interface port of a plurality of interface ports of a memory device, detecting a second host system connected to a second interface port of the plurality of interface ports, allocating a first range of logical block addresses (LBA) to one or more virtual functions (VFs) assigned to the first host system, and allocating a second range of LBAs to one or more VFs assigned to the second host system, wherein the first host system is to access the first range of LBA of the memory device concurrently with the second host system accessing the second range of LBA of the memory device, and wherein the first range of LBAs is different than the second range of LBAs.

Abstract: An apparatus for transmitting data over a bus system, having a storage device for at least temporary storage of messages transmittable over the bus system. The apparatus is designed to check at least one message, stored in the storage device, for at least one criterion and to alter at least one portion of the message based on the check.

Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.

Abstract: Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing transceivers, receivers, and/or transmitters of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided via a plurality of transceivers of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.

Abstract: A Universal Serial Bus (USB) Type-C and power delivery port with scalable power architecture is disclosed. In one aspect, at least two circuits for a USB port are consolidated into a single integrated circuit (IC). At least one of the at least two circuits is part of a Type-C port controller (TCPC) group of circuits including sensors associated with detecting whether a voltage and current are present at pins of a USB receptacle. At least the other one of the at least two circuits is selected from a battery-related group of circuits including a battery charging circuit, an over-voltage protection circuit, and a conditioning circuit. The more circuitry integrated into the single IC the more readily scalable the end product is for a multi-port device. Additional circuitry such as a light emitting diode (LED) driver may also be included in the single IC.

Abstract: In one embodiment, a method for managing a smart network interface controller includes: sending a request for estimated resource requirements associated with the smart network interface controller to a baseboard management controller of the information handling system, the estimated resource requirements indicating estimated system resources likely to be required by emulated devices of the smart network interface controller; receiving the estimated resource requirements from the baseboard management controller; initializing the estimated system resources based on the estimated resource requirements; enumerating system resources for one or more additional devices of the information handling system; determining that the smart network interface controller is in a ready state; identifying actual resource requirements associated with the smart network interface controller indicating actual system resources required by the emulated devices of the smart network interface controller; and enumerating the actual system

Abstract: Embodiments herein describe on-demand packetization where data that is too large to be converted directly into data words (DWs) for a chip-to-chip (C2C) interface are packetized instead. When identifying a protocol word that is larger than the DW of the C2C interface, a protocol layer can perform packetization where a plurality of protocol words are packetized and sent as a transfer. In one embodiment, the protocol layer removes some or all of the control data or signals in the protocol words so that the protocol words no longer exceed the size of the DW. These shortened protocol words can then be mapped to DWs and transmitted as separate packets on the C2C. The protocol layer can then collect the portion of the control data that was removed from the protocol words and transmit this data as a separate packet on the C2C interface.

Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.

Abstract: A device for a serial bus system. The device includes a receiver for receiving a signal from a bus, in which for a message that is exchanged between user stations of the bus system, the bus states of a signal received from the bus in the first communication phase differ from bus states of the signal received in the second communication phase. The receiver generates a digital signal based on the received signal, and outputs the signal to a communication control device to evaluate the data. The receiver uses a first reception threshold and a second reception threshold in the second communication phase to generate the digital signal. The second reception threshold has a negative voltage value or has a voltage value that is greater than the largest voltage value that is driven by a user station of the bus system for a bus state in the second communication phase.

Abstract: A serial communications bus system comprising a plurality of end users arranged to transmit data on a common data bus, each end user provided with a bus arbiter, physically separate from the respective end user, configured to define, for that end user, a cycle of transmission enable intervals whereby the end user may transmit data on the data bus and transmission disable intervals whereby the end user may not transmit data on the data bus.

Abstract: A method of acquiring data, a computer program product for implementing the method, a system for acquiring data, and a vehicle including the system. The method includes determining one or more data types and virtual channels required for one or more applications. The method also includes allocating a plurality of circular buffers in memory according to the determined data type(s) and virtual channel(s). One or more of the circular buffers are allocated to safety data lines. The remaining circular buffers are allocated to functional data lines. The method further includes storing at least one functional data line in a circular buffer allocated to functional data lines according to a data type and virtual channel of the functional data line. The method also includes storing at least one safety data line in a circular buffer allocated to safety data lines.

Abstract: A quantum computing service includes connections to one or more quantum hardware providers that are configured to execute quantum circuits using quantum computers based on one or more quantum technologies. The quantum computing service also includes at least one edge computing device located adjacent to a quantum computer at one of the quantum hardware provider facilities. The edge computing device is configured to execute classical computing portions of a hybrid algorithm in coordination with the quantum computer, which executes quantum computing portions of the hybrid algorithm. Results of the execution of the hybrid algorithm are automatically stored to a data storage service accessible to the customer.

Abstract: Methods and apparatus for efficient data transmit and receive operations using polling of memory queues associated with interconnect fabric interface. In one embodiment, Non-Transparent Bridge (NTB) technology used to transact the data transmit/receive operations and a hardware accelerator card used implement a notification mechanism in order to optimize of receive queue polling are disclosed. The accelerator card comprises a notification address configured to signal the presence of data, and a notification acknowledgement region configured to store flags associated with memory receive queues. In one implementation, the interconnect fabric is based on PCIe technology, including up to very large fabrics and numbers of hosts/devices for use in ultra-high performance applications such as for example data centers and computing clusters.

Abstract: Embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., SOC) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. The unsuccessful arbitration attempt by the integrated circuit may delay the transmission of the data packet until the multi-drop bus becomes available for the integrated circuit to send the data packet. The data packet includes a data field to include time delay information caused by the unsuccessful arbitration attempt. A receiving integrated circuit may determine the time that the data packet would have been sent out from the transmitting integrated circuit absent the unsuccessful arbitration attempt based on the delay information. Embodiments also relate to a synchronization generator circuit in an integrated circuit that generates timing signals indicating times at which periodic events occur at another integrated circuit.

Abstract: Battery management systems with dual CAN messaging. In at least one embodiment of a battery management system (BMS) of the present disclosure, the BMS comprises at least two, dual, controller area network (CAN) transceivers, wherein a first CAN transceiver is for a vehicle bus and a second CAN transceiver is for a charger bus, and a computer program operable to communicate with the two, dual, CAN transceivers to toggle back and forth between vehicle intended, and charger intended, messaging states to improve battery operating efficiency.

Abstract: A system includes a programmable logic control (PLC) module, an input/output (IO) network bus coupled to the PLC module and provided at facets of a mainframe. A first process chamber attached to a first facet of the facets. A chamber interface IO sub-module is attached to the first facet and coupled to the IO network bus and to a process chamber IO controller of the first process chamber. The chamber interface IO sub-module is to: convert interlock relay signals, received via dry contact exchange with the process chamber IO controller, to digital signals; combine the digital signals into network packets adapted for communication using a protocol of the IO network bus; and transmit the network packets to the PLC module over the IO network bus.

Abstract: The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data. The protocol conversion unit generates the second data by converting the first data from the first protocol to the second protocol. The slave interface detects errors in the copy data based on the error detection code. The slave interface also generates the first verification data by performing a conversion from one of the first protocol or the second protocol to the other for one of the second data or copy data. In addition, the slave interface compares the second verification data with the first verification data, using the other of the second data or copy as the second verification data.