Patents Examined by Christopher B. Shin
  • Patent number: 11914551
    Abstract: The present application discloses a pre-reading method and system of a kernel client, and a computer-readable storage medium. The method includes: receiving a reading request for a file and determining whether the reading of the file is continuous; if the reading of the file is discontinuous, generating a head node of a file inode, and constructing a linked list embedded in the head node; determining whether the file includes a reading rule for the file, and if the file includes the reading rule for the file, acquiring, based on the reading rule, the number of reading requests for the file and a reading offset corresponding to each request, generating a map route based on the number of reading requests and corresponding reading offsets, and storing the map route in the linked list; and executing pre-reading based on the linked list.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: February 27, 2024
    Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
    Inventor: Yamao Xue
  • Patent number: 11907040
    Abstract: The processor system includes a processor coupled to a memory having a plurality of memory banks and a region configurable as a heap region. At least one memory bank is allocated to the heap region dependent on a predetermined memory size required for execution of at least one cryptographic operation. At least one further memory bank is allocated to the heap region. The processor system may switch between first and second operating states. The first operating state has a lower power consumption than the second operating state. The processor system switches between a first and second operating mode by setting at least one memory bank and at least one further memory bank to an active state. The processor system switches between the second and first operating mode by setting at least one memory bank to a retention state and the at least one further memory bank to a power-down state.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: February 20, 2024
    Assignee: NXP USA, Inc.
    Inventors: Doru Cristian Gucea, Teodor Cosmin Grumei, Andrei Istodorescu
  • Patent number: 11907814
    Abstract: A system and method for machine learning. The system includes a GPU with a GPU memory, and a key value storage device connected to the GPU memory. The method includes, writing, by the GPU, a key value request to a key value request queue in a input-output region of the GPU memory, the key value request including a key. The method further includes reading, by the key value storage device, the key value request from the key value request queue, and writing, by the key value storage device, in response to the key value request, a value to the input-output region of the GPU memory, the value corresponding to the key of the key value request.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: February 20, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo Hwan Lee, Yang Seok Ki
  • Patent number: 11892955
    Abstract: System and method for analyzing CXL flits at read bypass detection logic to identify bypass memory read requests and transmitting the identified bypass memory read requests over a read request bypass path directly to a transaction/application layer of the CXL memory controller, wherein the read request bypass path does not include an arbitration/multiplexing layer and a link layer of the CXL memory controller, thereby reducing the latency inherent in a CXL memory controller.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: February 6, 2024
    Assignee: Microchip Technology Inc.
    Inventors: Sanjay Goyal, Larrie Simon Carr, Patrick Bailey
  • Patent number: 11886737
    Abstract: A memory device can include a plurality of memory cells for storing data, a memory interface configured to store and retrieve data at the plurality of memory cells, a logic unit comprising digital circuitry configured to perform mathematic and logic operations, and a control circuitry configured to control operation of the memory device.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: January 30, 2024
    Assignee: Infineon Technologies AG
    Inventor: Prakash Balasubramanian
  • Patent number: 11886750
    Abstract: A system and method employing a distributed hardware architecture, either independently or in cooperation with an attendant data structure, in connection with various data processing strategies and data analytics implementations are disclosed. A compute node may be implemented independent of a host compute system to manage and to execute data processing operations. Additionally, an unique algorithm architecture and processing system and method are also disclosed. Different types of nodes may be implemented, either independently or in cooperation with an attendant data structure, in connection with various data processing strategies and data analytics implementations.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: January 30, 2024
    Inventors: Robert Bismuth, Mike Stengle
  • Patent number: 11880316
    Abstract: Example methods and systems for input output (IO) request handling based on tracking information are described. One example may involve a computer system configuring, in a cache, a zero-filled logical memory page that is mappable to multiple logical block addresses of a virtual disk. In response to detecting a first IO request to perform zero writing at a logical block address, the computer system may store tracking information indicating that zero writing has been issued. In response to detecting a second IO request to perform a read at the logical block address, the computer system may determine that that zero writing has been issued for the logical block address based on the tracking information. The zero-filled logical memory page may be fetched from the cache to respond to the second IO request, thereby servicing the second IO request from the cache instead of the virtual disk.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: January 23, 2024
    Assignee: VMware, Inc.
    Inventor: Kashish Bhatia
  • Patent number: 11875059
    Abstract: According to one embodiment, a memory system connectable to a host via each of a first bus and a second bus includes a nonvolatile memory and a controller. The controller stores first data that is necessary for responding to a management command for acquiring a status of the memory system in a first volatile memory before causing the memory system to transition to a low power mode. The controller causes the memory system to transition to the low power mode by stopping supply of power to each of components of the controller except for a first interface circuit connected to a first bus, a second interface circuit connected to a second bus, and the first volatile memory, and stopping the supply of power to the nonvolatile memory.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: January 16, 2024
    Assignee: Kioxia Corporation
    Inventor: Hisashi Otani
  • Patent number: 11868279
    Abstract: Designs for a rackmount chassis having multiple card slots are presented herein. In one example, an apparatus includes a chassis configured to mount into a server rack, including a plurality of peripheral card slots, and a plurality of status lights configured to provide indications of operational status for an associated slot. The chassis further includes switch circuitry, including at least three switch elements, configured to couple the slots, wherein a first portion of ports on each of the switch elements is coupled to corresponding slots, a second portion of the ports on each of the switch elements is coupled to external ports of the chassis, and a third portion of the ports on each of the switch elements is coupled to at least another among the switch elements. The chassis may further include a plurality of external ports on the chassis communicatively coupled to the slots through the switch circuitry.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: January 9, 2024
    Assignee: Liqid Inc.
    Inventors: Christopher R. Long, Andrew Rudolph Heyd, Brenden Rust
  • Patent number: 11868280
    Abstract: A system can include a plurality of sequencers each configured to provide a number of sequenced output signals responsive to assertion of a respective sequencer enable signal provided thereto. The system can include chaining circuitry coupled to the plurality of sequencers. The chaining circuitry can comprise logic to: responsive to assertion of a primary enable signal received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; and responsive to deassertion of the primary enable signal, assert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Keith A Benjamin, Thomas Dougherty
  • Patent number: 11868624
    Abstract: An electronic device is provided. A computing system includes a storage device and a host. The storage device includes a memory device including a write protection area. The host performs an operation of providing, to the storage device, a first request regarding security write and write data in parallel with an operation of generating a host authentication code based on the write data and a key shared with the storage device.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: January 9, 2024
    Assignee: SK hynix Inc.
    Inventor: Gun Wook Lee
  • Patent number: 11860799
    Abstract: Described apparatuses and methods enable a receiver of requests, such as a memory device, to modulate the arrival of future requests using a credit-based communication protocol. A transmitter of requests can be authorized to transmit a request responsive to possession of a credit corresponding to the communication request. In these situations, if the transmitter has exhausted a supply of credits, the transmitter waits until a credit is returned before transmitting another request. The receiver of the requests can manage credit returns based on whether a request queue has space to receive another request. Further, the receiver can delay a credit return based on how many requests are pending at the receiver, even if space is available in the request queue. This delay can prevent an oversupply of requests from developing downstream of the request queue. Latency, for instance, can be improved by managing the presence of requests that are downstream.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: January 2, 2024
    Assignee: Micron Technologies, Inc.
    Inventors: Nikesh Agarwal, Chandana Manjula Linganna
  • Patent number: 11860797
    Abstract: Restricting peripheral device protocols in confidential compute architectures, the method including: receiving a first address translation request from a peripheral device supporting a first protocol, wherein the first protocol supports cache coherency between the peripheral device and a processor cache; determining that a confidential compute architecture is enabled; and providing, in response to the first address translation request, a response including an indication to the peripheral device to not use the first protocol.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: January 2, 2024
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Philip Ng, Nippon Raval, David A. Kaplan, Donald P. Matthews, Jr.
  • Patent number: 11853234
    Abstract: A host can include a programmable network interface card (NIC) or “Smart NIC” which accesses host-local drives hidden from a host processor. One configuration can include a switch with a one logical partition including the NIC as a root complex (RC) and the local drives as end points (EPs), and with another logical partition including the host processor as an RC and the NIC as an EP. A second configuration can include the NIC and switch directly connected to the host processor with an access control component (ACC) configured on switch ports connected to the local drives. A third configuration can include the NIC and local drives directly connected to the host processor with the ACC configured on host processor ports connected to the local drives. The NIC can use a multi-layer driver to communicate with the ACC and local drives hidden behind the ACC.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: December 26, 2023
    Assignee: Dell Products L.P.
    Inventors: Boris Glimcher, Aric Hadav, Amitai Alkalay
  • Patent number: 11847049
    Abstract: The total memory space that is logically available to a processor in a general-purpose graphics processing unit (GPGPU) module is increased to accommodate terabyte-sized amounts of data by utilizing the memory space in an external memory module, and by further utilizing a portion of the memory space in a number of other external memory modules.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: December 19, 2023
    Assignee: Alibaba Damo (Hangzhou) Technology Co., Ltd
    Inventors: Yuhao Wang, Dimin Niu, Yijin Guan, Shengcheng Wang, Shuangchen Li, Hongzhong Zheng
  • Patent number: 11836387
    Abstract: A multi-stream memory system includes an in-device data processor including a first data processing engine and a second data processing engine, a controller processor, and a processor memory coupled to the controller processor, wherein the processor memory has stored thereon instructions that, when executed by the controller processor, cause the controller processor to perform: identifying a stream ID of an input stream, identifying the first data processing engine as being associated with the stream ID based on a stream assignment table, and applying the first data processing engine to the input stream to generate processed data.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: December 5, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jing Yang, Jingpei Yang, Rekha Pitchumani
  • Patent number: 11836096
    Abstract: Described apparatuses and methods relate to a memory-flow control register for a memory system that may support a nondeterministic protocol. To help manage the flow of memory requests in a system, a memory device can include logic, such as a hardware register, that can store values indicative of a total number of memory requests that are serviceable by the memory device at a time. The logic can be configured by device manufacturers during assembly. The manufacturers can determine the limits or capabilities of the system, based on the components and structures, and publish the capabilities, including QoS, based on the limits. When the memory device is connected to a host, the host can read the values and limit the number of memory requests sent to the device based on the values. Accordingly, the memory-flow control register can improve latency and bandwidth in accessing a memory device over an interconnect.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: December 5, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Nikesh Agarwal, Robert Walker, Laurent Isenegger
  • Patent number: 11829251
    Abstract: Disclosed methods and systems leverage resources in a storage management system to restore a selected backup to a production site. The backup is partitioned into blocks with associated signatures. The production site may have blocks that have not changed from when the backup occurred, so those blocks do not need to be restored. Block signatures from the production site are compared with block signatures from the incremental backup to identify blocks that need to be restored. Efficiency may be achieved by synchronizing the replacement blocks from more easily accessible location where available before synchronizing from less accessible locations. In some embodiments, a user may specify the location of the site with the replacement blocks.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: November 28, 2023
    Assignee: Commvault Systems, Inc.
    Inventors: Manoj Kumar Vijayan, Saurabh Agrawal
  • Patent number: 11822490
    Abstract: A method for communicating with a device may include running, at a device, an operating system, communicating, using a first function of an interconnect, with the device, and communicating, using a second function of the interconnect, with the operating system. The operating system may include communication logic, and the communicating with the operating may include communicating with the communication logic. The communication logic may one or more terminal support drivers, and the communicating with the communication logic may include communicating with the one or more terminal support drivers using a terminal application. The terminal application may run on a host. The second function of the interconnect may be configured to operate with a controller. The communicating with the operating system may include communicating with the operating system based on a privilege information. The host may be a management controller.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: November 21, 2023
    Inventors: Rajinikanth Pandurangan, Changho Choi, Yang Seok Ki, Sungwook Ryu
  • Patent number: 11816058
    Abstract: A method, apparatus, and device for dynamically modifying a PCH PCIE root port where an onboard VGA is located, and a readable storage medium. The current item may be determined at a PEI phase by reading a GPIO interface, and a target PCH PCIE root port used by the item is further determined; then configuration information is acquired, and a target onboard VGA is found and initialized; because a video bridge configuration file defined in an SDL file is saved in a structure of a temporary file when code is compiled, in the method, the value of a target member of the structure is modified as the port number of the target PCH PCIE root port at a DXE phase, so that a video bridge is switched to the target PCH PCIE root port.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: November 14, 2023
    Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Huijuan Qian, Bing Wang, Fanyi Yao