Patents Examined by Christopher B. Shin
  • Patent number: 11119682
    Abstract: Examples include compressed extent versions. Examples may create an empty target virtual volume tree having a tree structure of a source virtual volume tree of a source storage system, the source virtual volume tree comprising source base and source snapshot virtual volumes, each representing respective versions of a plurality of extents, wherein each of the extents corresponds to a different portion of an address space of the source base virtual volume. Examples may include compressed extent collections, each comprising a compressed representation of multiple populated versions of a single extent from the source base and snapshot virtual volumes, the multiple populated versions compressed relative to one another.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: September 14, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Ayman Abouelwafa, Salil Gokhale, Srinivasa D. Murthy
  • Patent number: 11113001
    Abstract: In some examples, fabric driven NVMe subsystem zoning may include receiving, from a non-volatile memory express (NVMe) Name Server (NNS), a zoning specification that includes an indication of a host that is to communicate with a given NVMe subsystem of an NVMe storage domain. Based on the zoning specification, the host may be designated as being permitted to connect to the given NVMe subsystem of the NVMe storage domain. An NVMe connect command may be received from the host. Based on the designation and an analysis of the NVMe connect command, a connection may be established between the given NVMe subsystem of the NVMe storage domain and the host.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 7, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Asutosh Satapathy, Komateswar Dhanadevan, Krishna Babu Puttagunta, Vivek Agarwal, Rupin T. Mohan, Govind Chandru Rathod
  • Patent number: 11099987
    Abstract: A method comprising identifying a portion of data in a first memory component to be written to a managed unit of a second memory component and determining whether an additional portion of data in the first memory component associated with the managed unit is stored at the cache memory. The method further includes generating a bit mask identifying locations of the managed unit associated with the portion of data and the additional portion of data and performing, based on the bit mask, a write operation comprising the portion of data and the additional portion of data to the managed unit of the second memory component.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Trevor C. Meyerowitz, Dhawal Bavishi, Fangfang Zhu
  • Patent number: 11093136
    Abstract: Example systems relate to system call acceleration. A system may include a processor and a non-transitory computer readable medium. The non-transitory computer readable medium may include instructions to cause the processor to run a plurality of benchmarks for a hardware configuration. The non-transitory computer readable medium may further include instructions to determine a benchmark matrix based on the plurality of benchmarks. The non-transitory computer readable medium may include instructions to determine an input/output (I/O) bandwidth ceiling for the hardware configuration based on the benchmark matrix. Additionally, the non-transitory computer readable medium may include instructions to determine a performance threshold of an I/O access parameter for the hardware configuration based on the bandwidth ceiling.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: August 17, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Tadeu Marchese, Raphael Gay, Taciano Perez
  • Patent number: 11093416
    Abstract: A memory system supporting programmable selective access to subsets of parallel-arranged memory chips for efficient memory accesses is disclosed. A memory controller is programmable to selectively control a number of parallel-arranged memory chips in the memory system activated in a grouping for a memory access based on a memory access policy. The memory access policy is based on the number of memory chips to be activated to achieve the desired data line size for a given memory access. This programmability of the memory controller is made possible by separate dedicated chip select lines being coupled to each memory chip. Being able to only activate a subset of the memory chips for a memory access allows conservation of data bus bandwidth and power that would otherwise by consumed by asserting unused data on the data buses.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: August 17, 2021
    Assignee: Qualcomm Intelligent Solutions, Inc
    Inventors: David Stewart Dunning, Shekhar Yeshwant Borkar, Nitin Yeshwant Borkar, Matthew Scott Radecic
  • Patent number: 11086528
    Abstract: There are provided a memory controller and a memory system having the same. The memory controller includes: a command generator configured to generate a command in response to a request received from a host; a throttling manager configured to activate or inactivate a delay signal by comparing a current throughput of data that is being currently processed in a memory system and a request throughput of data that is to be processed in the memory system; and a completion signal output circuit configured to delay an output of a completion signal with respect to the request when the delay signal is activated, and outputs the completion signal when the delay signal is inactivated.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: August 10, 2021
    Assignee: SK hynix Inc.
    Inventors: Seok Hoon Jung, Min Seong Chae
  • Patent number: 11080217
    Abstract: A method of operating a storage device includes receiving, from a host, a first packet containing a buffer address indicating a location of a data buffer selected from among a plurality of data buffers in the host, parsing the buffer address from the first packet, and transmitting a second packet containing the buffer address to the host in response to the first packet.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: August 3, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Min Lee, Sung-Ho Seo, Hwa-Seok Oh, Kyung-Phil Yoo, Seong-Yong Jang
  • Patent number: 11074185
    Abstract: Provided are a computer program product, system, and method for adjusting a number of insertion points used to determine locations in a cache list at which to indicate tracks. Tracks added to the cache are indicated in a cache list. The cache list has a least recently used (LRU) end and a most recently used (MRU) end. In response to indicating in a cache list an insertion point interval number of tracks in the cache in a cache list, setting an insertion point to indicate one of the tracks of the insertion point interval number of tracks indicated in the cache list. Insertion points to tracks in the cache list are used to determine locations in the cache list at which to indicate tracks in the cache in the cache list.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: July 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Patent number: 11068196
    Abstract: A method for performing a backup operation includes obtaining a restoration request, and in response to the restoration request: identifying a first set of backups, wherein each backup in the first set of backups is associated with requested data, mounting the first set of backups from the backup storage system, performing data mining on the first set of backups to obtain a hierarchical structure, providing a set of options to a client based on the hierarchical structure, obtaining a selection from the client, wherein the selection is a portion of the set of options, obtaining selected content based on the selection, wherein the selected content is in a source format, converting the selected content from a source format to a target format to obtain target formatted user-specified content, and initiating a transfer of the target-formatted user-specified content to a cloud-based service.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: July 20, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Aneesh Kumar Gurindapalli, Deepthi Urs, Mahesh Reddy Appireddygari Venkataramana, Swaroop Shankar DH
  • Patent number: 11068421
    Abstract: The present invention provides a memory device including a connector and a flash memory controller. The connector is configured to connect to a first host and a second host. The flash memory controller is configured to select one of the first host and the second host based on a selection signal, and the flash memory controller only processes commands from the selected one of the first host and the second host, and accesses a flash memory module based on the commands.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: July 20, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Hung-Pin Tsai, Chih-Chien Lin, Chien-An Chen
  • Patent number: 11068194
    Abstract: Disclosed herein are systems and method for storing and managing states of a computing device. In one aspect, an exemplary method comprises determining an initial state of the computing device, wherein the initial state includes states of all storage sectors associated with the computing device, storing the determined initial state in an initial blocks storage, for each new state that corresponds to a respective point in time subsequent to a time at which the initial state was determined, creating a snapshot, where the created snapshot includes a difference between the initial state and the new state, for each created snapshot, identifying a set of changed blocks that are in storage, and storing the changed blocks of data to a changed blocks storage, and creating a snap-map for any number of consecutive changes based on the sets of changed blocks corresponding to the respective consecutive changes.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 20, 2021
    Assignee: Acronis International GmbH
    Inventors: Oleg Melnikov, Vladimir Strogov, Alexey Sergeev, Serguei Beloussov, Alexey Dod, Stanislav Protasov
  • Patent number: 11068195
    Abstract: The systems and methods of distributed backup on a private network, comprising: establishing a secure and encrypted private network with one or more profile computing devices; establishing a whitelist of trusted profiles on a first profile computing device; selecting two or more profiles from the whitelist to backup information from the first profile computing device; tracking any updates to the network address of the selected profiles for backup; tracking information on remote profile computing devices that originated from the first profile computing device; sending differential information for backup that does not exist on other remote profile computing devices to the selected profile computing devices.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: July 20, 2021
    Assignee: Whitestar Communications, Inc.
    Inventor: Billy Gayle Moon
  • Patent number: 11068165
    Abstract: An open block management apparatus, system, and method for non-volatile memory devices is disclosed herein, providing improved performance for namespace-based host applications. The namespace identifier is applied to determine the open blocks to which to direct data from storage commands. One benefit of the disclosed technique is fewer de-fragmentation operations and more efficient memory garbage collection. Another benefit is the ability to secure private allocations of physical memory without needing to assign a partition or implement hardware isolation.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: July 20, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Eran Sharon, Shay Benisty, Ariel Navon, Judah Gamliel Hahn
  • Patent number: 11055179
    Abstract: Some examples relate generally to computer architecture software for information security and, in some more particular aspects, to tree-based snapshots and detecting malware therein.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: July 6, 2021
    Assignee: RUBRIK, INC.
    Inventor: Sahil Chauhan
  • Patent number: 11036656
    Abstract: An industrial automation system employing a mesh topology of input/output allows flexibility in pairing field devices and controllers though the I/O mesh. Field devices can be connected to the geographically closest I/O module channel without regard to the location of the necessary controller. Modular prefabrication and deployment of the I/O modules becomes less complex and less time consuming thereby reducing costs.
    Type: Grant
    Filed: April 7, 2019
    Date of Patent: June 15, 2021
    Assignee: Honeywell International Inc.
    Inventors: Paul Francis McLaughlin, Christopher Paul Ladas, Angela Lee Lordi, James Michael Schreder, Stanley Robert Gorzelic
  • Patent number: 11036421
    Abstract: A memory system includes a memory device including plural memory blocks divided into a system region, a user data region and a reserved region. The system region includes a first block storing original firmware and a second block storing copied firmware, and the reserved region includes a dedicated test block having an operational characteristic that substantially the same as that of the second block. The memory system includes a controller configured to access the dedicated test block for determining a status of the second block based on an operation state of the dedicated test block, and to update both the dedicated test block and the second block based on the status of the second block.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventors: Jeen Park, Jung-Ae Kim, Duk-Rae Lee
  • Patent number: 11023376
    Abstract: A multiprocessor system includes a plurality of nodes and at least one memory, each node containing at least one processor; a first cache configured to store a plurality of first cache lines, the first cache being private to at least one node from among the plurality of nodes; and a second cache configured to store a plurality of second cache lines, the second cache being at a higher level than the first cache, wherein at least one of the first cache lines includes a first associated pointer pointing to a location of one of the second cache lines, and wherein at least one of the second cache lines includes a second associated pointer pointing to a location of one of the first cache lines.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: June 1, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Erik Ernst Hagersten
  • Patent number: 10996881
    Abstract: Provided herein may be a storage device and a method of operating the storage device. The storage device may include a memory device including buffer blocks and main blocks, and a memory controller configured to control the memory device. The memory controller may include: a buffer block controller configured to control the memory device to store, in at least one of the main blocks, data stored in at least one of the buffer blocks; a mapping table manager configured to generate a P2P mapping table including mapping information between a buffer address that is a physical address of the at least one buffer block and a main address that is a physical address of the at least one main block; and a read operation controller configured to control, when a read request is received, the memory device to read the data based on the main address or the buffer address.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: May 4, 2021
    Assignee: SK hynix Inc.
    Inventors: Seung Wan Jung, So Hee Kim, Seung Ok Han
  • Patent number: 10990539
    Abstract: A memory system includes a memory device and a controller. The memory device includes first and second memory groups. The controller includes a resource controller and first and second flash translation layer (FTL) cores. Each of the first and second FTL cores manages a plurality of logical addresses (LAs) that are mapped, respectively, to a plurality of physical addresses (PAs) of a corresponding memory group. The resource controller determines LA use rates of the first and second FTL cores, selects a source FTL core and a target FTL core from the first and second FTL cores using the LA use rates, and balances the LA use rates of the source FTL core and the target FTL core by moving data stored in storage spaces associated with a portion of the LAs from the source FTL core to storage spaces associated with the target FTL core.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: April 27, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Patent number: 10990325
    Abstract: A write control method, an associated data storage device and the controller thereof are provided. The write control method includes: receiving one or more commands from a host device and executing the one or more commands, and performing determining operations to generate determining results; in response to the determining results, starting performing write collection; collecting and handling one or more write commands to buffer data of the one or more write commands through a buffer memory, and performing other determining operations to generate other determining results; in response to the other determining results, according to a quantity of one or more collected and handled write commands, determining whether data thereof has filled up a write buffer region of the buffer memory; and in response to the data having filled up the write buffer region, flushing the write buffer region to write the data therein into a non-volatile memory.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: April 27, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Yu-Han Hsiao, Yang-Chih Shen, Huan-Jung Yeh