Abstract: A method includes setting an order of input-output channels of a column of a first chiplet of multiple chiplets of a chiplet-based system, wherein one or more of the multiple chiplets include field-configurable input-output channels arranged at a periphery of the chiplets; and programming a second chiplet of the multiple chiplets to change an order of input-output channels of a column of the second chiplet to match the order of input-output channels of the column of the first chiplet.

Abstract: A memory structure including three-dimensional NOR memory strings and method of fabrication is disclosed. In one embodiment, a memory system includes a set of memory modules of quasi-volatile memory circuits interconnected to a memory controller and having a set of memory ports. The memory system includes a first processor port, a second processor port, and one or more DIMM interface ports to be coupled to respective processors for providing access to the set of memory modules. In another embodiment, an artificial intelligence (AI) computing system includes a set of memory modules of quasi-volatile memory circuits interconnected to a memory controller and an arithmetic function block performing multiply and accumulate functionalities using data stored in the memory modules. The set of memory modules are accessed to perform read, write and erase memory operations in a rotating manner in each computing cycle.

Abstract: A method is implemented by a PCC decoder and comprises: receiving, by the PCC decoder, a point cloud bitstream; performing, by the PCC decoder, buffering of the point cloud bitstream based on a time, the performing comprising determining the time based on a delay and a delay offset; and decoding, by the PCC decoder, the point cloud bitstream based on the buffering. A method is implemented by a PCC decoder and comprises: receiving, by the PCC decoder, a point cloud bitstream; performing, by the PCC decoder, buffering of the point cloud bitstream based on a delay, the delay is based on a first delay and a second delay; and decoding, by the PCC decoder, the point cloud bitstream based on the buffering.

Abstract: An external nonvolatile memory device that includes a rewritable nonvolatile memory and a CMOS interface is disclosed. The interface includes a clock signal which is input to the external nonvolatile memory device. This clock signal is multiplied by an integer to create a memory serdes clock which is used to clock outgoing data. The memory serdes clock is also used to create a clock that is used to clock the incoming data from the main processing device. The external nonvolatile memory device also includes an encryption/decryption block that encrypts data read from the nonvolatile memory before it is transmitted over the interface, and decrypts data received from the interface before storing it in the nonvolatile memory. The encryption/decryption block may utilize a stream cipher.

Abstract: A memory apparatus embedded with a computing function and an operation method thereof are provided. The memory apparatus includes a memory array, a plurality of data flow controllers, a plurality of computation circuits, a data bus, and a control logic circuit. The memory array includes a plurality of block groups having a plurality of memory blocks. Each of the data flow controllers selects a transmission path of data of each memory block according to a corresponding one of the data flow control signals. In a computation mode, the computation circuit computes first data from the corresponding memory block. In a normal mode, second data is transmitted between the data bus and the corresponding memory block. The data flow controller transmits the first data from the corresponding memory block to the computation circuit according to the data flow control signal provided by the control logic circuit to compute the first data.

Abstract: A storage product manufactured as a standalone computer component and installed in a computing system to implement an internet application. The storage product includes a network interface, a host interface, computing circuits, and a local storage device having a storage capacity accessible via the network interface. A data generator is connected to the network interface. A local host system is connected to the host interface to control access, made via the network interface. The data generator can send bulk data to the network interface. The computing circuits can generate derived data from the bulk data and store the derived data and/or the bulk data in the local storage device. A central server and/or a user device can connect over internet via to the network interface of the storage product to access the derived data and/or the bulk data.

Abstract: A method is disclosed of copy-free, non-disruptive conversion of a storage volume from a first access protocol to a distinct second access protocol. In a preparatory step a destination volume accessible according to the second access protocol is created. A pairing of a token and a handle is created, the token representing data content of the source volume, the handle being associated with the token and usable to represent the source volume according to the second protocol. In response to a subsequent copy-with-handle command, and based on the pairing of the handle with the token, metadata of the destination volume is populated to reference, without copying, the underlying stored data, the destination volume thereafter functioning as the storage volume accessed using the second protocol.

Abstract: Zero skipping sparsity techniques for reduced data movement between memory and accelerators and reduced computational workload of accelerators. The techniques include detection of zero and near-zero values on the memory. The non-zero values are transferred to the accelerator for computation. The zero and near-zero values are written back within the memory as zero values.

Abstract: An integrated circuit includes protected container access control logic to perform a set of access control checks and to determine whether to allow a device protected container module (DPCM) and an input and/or output (I/O) device to communicate securely through one of direct memory access (DMA) and memory-mapped input/output (MMIO). The DPCM and the I/O device are allowed to communicate securely if it is determined that at least the DPCM and the I/O device are mapped to one another, an access address associated with the communication resolves into a protected container memory, and a page of the protected container memory into which the access address resolves allows for the aforementioned one of DMA and MMIO. In some cases, a Security Attributes of Initiator (SAI) or security identifier may be used to obtain a DPCM identifier or attest that access is from a DPCM mapped to the I/O device.

Abstract: A firmware is configured with a firmware management protocol (“FMP”) capable of updating a firmware logo image and a firmware logo image volume is defined within a firmware for storing a firmware logo image. A firmware logo image updater executing on a computing device receives a UEFI capsule that contains a firmware logo image. The firmware logo image updater stores the UEFI capsule in a UEFI system partition on a computer-readable storage medium accessible to the computing device. Upon a reboot of the computing device, the FMP is executed. The FMP retrieves the UEFI capsule from the UEFI system partition. The FMP then updates the firmware logo image volume with the firmware logo image stored in the UEFI capsule.

Abstract: A system includes a memory device associated with a logical address space, and a processing device, operatively coupled to the memory device, to perform operations including providing, to a host system, power safety capability information for the logical address space, obtaining, from the host system, a power safety configuration for a partition of the logical address space, and providing, to the host system, an acknowledgement of receipt of the power safety configuration.

Abstract: A system that incorporates the subject disclosure may include, for example, a method that includes identifying a plurality of devices associated with a computing device, identifying status information from each device of the plurality of devices, and identifying presentation features for each device of the plurality of devices. The method further includes receiving presentation information indicating a setting to present first status information from a first device of the plurality of devices via a selected device of the plurality of devices, wherein the first status is presented on the selected device by a selected presentation feature of the selected device. Additional embodiments are disclosed.

Abstract: An electronic device is provided. The electronic device includes a memory and an integrated circuit. The integrated circuit includes an address remapping unit. The memory includes multiple memory pages. The integrated circuit converts multiple virtual addresses into multiple physical addresses in sequence. The address remapping unit prefetches a first physical address corresponding to a first virtual address if a second virtual address exceeds a preset offset. The first virtual address is in a different memory page from the second virtual address. The second virtual address is currently processed. The multiple virtual addresses include the first and second virtual addresses.

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

Abstract: Apparatuses and methods can be related to placing memory in a computing system. The memory modules can be placed in memory slots to couple the memory modules to the computing system. The memory modules and/or the memory slots can have thermal qualities which can be utilized to determine which of the memory modules are placed on which of the memory slots.

Abstract: This document describes apparatuses and techniques for implementing data masking with pulse amplitude modulation (PAM) encoded signals of a memory circuit. In various aspects, a data mask function of a memory controller may use an unassigned or prohibited PAM signaling state for a set of data lines to indicate data masking to a memory device for a group of data bits. For example, the data mask function may alter a PAM symbol or signal level for at least one data line from a low-voltage state (L) or mid-voltage state (M) state to a high-voltage state (H), resulting in a PAM signaling state for the set of data lines that corresponds data mask indication for the group of data bits. By so doing, the data mask function may indicate data masking for the group of bits without a dedicated data mask signal line, which may enable improved per-line memory bandwidth.

Abstract: An out-of-order buffer includes an out-of-order queue and a controlling circuit. The out-of-order queue includes a request sequence table and a request storage device. The controlling circuit receives and temporarily stores the plural requests into the out-of-order queue. After the plural requests are transmitted to plural corresponding target devices, the controlling circuit retires the plural requests. The request sequence table contains m×n indicating units. The request sequence table contains m entry indicating rows. Each of the m entry indicating rows contains n indicating units. The request storage device includes m storage units corresponding to the m entry indicating rows in the request sequence table. The state of indicating whether one request is stored in the corresponding storage unit of the m storage units is recoded in the request sequence table. The storage sequence of the plural requests is recoded in the request sequence table.

Abstract: An event log management technique may include determining a new event associated with a storage device has occurred, determining a new event log can be stored in an event log chunk stored in an event log buffer, and deleting a number of old event logs starting from an oldest event log among old event logs of the event log chunk stored in the event log buffer if the new event log can be stored in the event log chunk stored in the event log buffer. The number of old event logs being deleted corresponds to a size of a new event log associated with the new event. The technique may also include storing the new event log starting at a start position of the oldest event log.

Abstract: Disclosed is an IO request pipeline processing device. The device mainly includes: an IO state buffer and a pipeline controller, wherein the IO state buffer includes multiple elements, for storing context information including a module calling sequence generated by a CPU; and the pipeline controller is configured to perform pipeline control on an IO request according to the context information. The device performs pipeline management on an IO processing state by arranging hardware modules, which shares the huge workload during an original CPU software control process, and also reduces the requirements for CPU design. At the same time, processing logic of the pipeline controller is triggered by the module calling sequence recorded in the IO state buffer, which may reduce the implementation power consumption and improve the implementation efficiency.

Abstract: There is provided an apparatus, method, and computer-readable medium. The apparatus comprises interconnect circuitry to couple a device to one or more processing elements and to one or more storage structures. The apparatus also comprises stashing circuitry configured to receive stashing transactions from the device, each stashing transaction comprising payload data and control data. The stashing circuitry is responsive to a given stashing transaction whose control data identifies a plurality of portions of the payload data, to perform a plurality of independent stashing decision operations, each of the plurality of independent stashing decision operations corresponding to a respective portion of the plurality of portions of payload data and comprising determining, with reference to the control data, whether to direct the respective portion to one of the one or more storage structures or whether to forward the respective portion to memory.