Abstract: Restricting peripheral device protocols in confidential compute architectures, the method including: receiving a first address translation request from a peripheral device supporting a first protocol, wherein the first protocol supports cache coherency between the peripheral device and a processor cache; determining that a confidential compute architecture is enabled; and providing, in response to the first address translation request, a response including an indication to the peripheral device to not use the first protocol.

Abstract: A host can include a programmable network interface card (NIC) or “Smart NIC” which accesses host-local drives hidden from a host processor. One configuration can include a switch with a one logical partition including the NIC as a root complex (RC) and the local drives as end points (EPs), and with another logical partition including the host processor as an RC and the NIC as an EP. A second configuration can include the NIC and switch directly connected to the host processor with an access control component (ACC) configured on switch ports connected to the local drives. A third configuration can include the NIC and local drives directly connected to the host processor with the ACC configured on host processor ports connected to the local drives. The NIC can use a multi-layer driver to communicate with the ACC and local drives hidden behind the ACC.

Abstract: The total memory space that is logically available to a processor in a general-purpose graphics processing unit (GPGPU) module is increased to accommodate terabyte-sized amounts of data by utilizing the memory space in an external memory module, and by further utilizing a portion of the memory space in a number of other external memory modules.

Abstract: A multi-stream memory system includes an in-device data processor including a first data processing engine and a second data processing engine, a controller processor, and a processor memory coupled to the controller processor, wherein the processor memory has stored thereon instructions that, when executed by the controller processor, cause the controller processor to perform: identifying a stream ID of an input stream, identifying the first data processing engine as being associated with the stream ID based on a stream assignment table, and applying the first data processing engine to the input stream to generate processed data.

Abstract: Described apparatuses and methods relate to a memory-flow control register for a memory system that may support a nondeterministic protocol. To help manage the flow of memory requests in a system, a memory device can include logic, such as a hardware register, that can store values indicative of a total number of memory requests that are serviceable by the memory device at a time. The logic can be configured by device manufacturers during assembly. The manufacturers can determine the limits or capabilities of the system, based on the components and structures, and publish the capabilities, including QoS, based on the limits. When the memory device is connected to a host, the host can read the values and limit the number of memory requests sent to the device based on the values. Accordingly, the memory-flow control register can improve latency and bandwidth in accessing a memory device over an interconnect.

Abstract: Disclosed methods and systems leverage resources in a storage management system to restore a selected backup to a production site. The backup is partitioned into blocks with associated signatures. The production site may have blocks that have not changed from when the backup occurred, so those blocks do not need to be restored. Block signatures from the production site are compared with block signatures from the incremental backup to identify blocks that need to be restored. Efficiency may be achieved by synchronizing the replacement blocks from more easily accessible location where available before synchronizing from less accessible locations. In some embodiments, a user may specify the location of the site with the replacement blocks.

Abstract: A method for communicating with a device may include running, at a device, an operating system, communicating, using a first function of an interconnect, with the device, and communicating, using a second function of the interconnect, with the operating system. The operating system may include communication logic, and the communicating with the operating may include communicating with the communication logic. The communication logic may one or more terminal support drivers, and the communicating with the communication logic may include communicating with the one or more terminal support drivers using a terminal application. The terminal application may run on a host. The second function of the interconnect may be configured to operate with a controller. The communicating with the operating system may include communicating with the operating system based on a privilege information. The host may be a management controller.

Abstract: A method, apparatus, and device for dynamically modifying a PCH PCIE root port where an onboard VGA is located, and a readable storage medium. The current item may be determined at a PEI phase by reading a GPIO interface, and a target PCH PCIE root port used by the item is further determined; then configuration information is acquired, and a target onboard VGA is found and initialized; because a video bridge configuration file defined in an SDL file is saved in a structure of a temporary file when code is compiled, in the method, the value of a target member of the structure is modified as the port number of the target PCH PCIE root port at a DXE phase, so that a video bridge is switched to the target PCH PCIE root port.

Abstract: A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device's logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.

Abstract: A device including an interface with peripherals includes a first interface that receives a request from a host, a second interface that periodically receives at least one first sample input from the peripherals in response to the request from the host, a memory that stores an active time table including a processing time of a sample input provided by each of the peripherals in each of a plurality of operating conditions respectively corresponding to different power consumptions, and a processing circuit that identifies at least one of the plurality of operating conditions based on the active time table and a period of the at least one first sample input.

Abstract: Semiconductor memory systems and architectures for shared memory access implements memory-centric structures using a quasi-volatile memory. In one embodiment, a memory processor array includes an array of memory cubes, each memory cube in communication with a processor mini core to form a computational memory. In another embodiment, a memory system includes processing units and one or more mini core-memory module both in communication with a memory management unit. Mini processor cores in each mini core-memory module execute tasks designated to the mini core-memory module by a given processing unit using data stored in the associated quasi-volatile memory circuits of the mini core-memory module.

Abstract: There is provided a communication apparatus comprising a connector that includes a plurality of signal lines and connects to an external recording device. The control unit performs control to determine whether a second signal has been input before a predetermined time period elapses since a first signal was output to the external recording device, the second signal indicating that the external recording device is compatible with a second transfer mode. In a case where it is determined that the second signal has been input, the control unit performs control to perform communication in the second transfer mode.

Abstract: A memory apparatus embedded with a computing function and an operation method thereof are provided. The memory apparatus includes a memory array, a plurality of data flow controllers, a plurality of computation circuits, a data bus, and a control logic circuit. The memory array includes a plurality of block groups having a plurality of memory blocks. Each of the data flow controllers selects a transmission path of data of each memory block according to a corresponding one of the data flow control signals. In a computation mode, the computation circuit computes first data from the corresponding memory block. In a normal mode, second data is transmitted between the data bus and the corresponding memory block. The data flow controller transmits the first data from the corresponding memory block to the computation circuit according to the data flow control signal provided by the control logic circuit to compute the first data.

Abstract: In a computer system, a processor and an I/O device controller communicate with each other via a coherence interconnect and according to a cache coherence protocol. Registers of the I/O device controllers are mapped to the cache coherent memory space to allow the processor to treat the registers as cacheable memory. As a result, latency of processor commands executed by the I/O device controller is decreased, and size of data stored in the I/O device controller that can be accessed by the processor is increased from the size of a single register to the size of an entire cache line.

Abstract: A method of operating a storage device includes receiving, from a host, a first packet containing a buffer address indicating a location of a data buffer selected from among a plurality of data buffers in the host, parsing the buffer address from the first packet, and transmitting a second packet containing the buffer address to the host in response to the first packet.

Abstract: A system and method are provided. In one example, a system is disclosed that includes a memory device and a first interface configured to connect with a first external device. The interface may include a device side that enables a first data exchange with the first external device and a system side that enables a second data exchange with the memory device, where the system side further enables an exchange of platform hints between the first interface and the memory device. The system may also include a hinting unit that populates the platform hints in an address bit.

Abstract: A method for accessing data in an external memory of a microcontroller, the microcontroller having an internal memory. The method includes: providing a classification data record in the internal memory, the classification data record for data stored in segments in the external memory including a segment-data classification for each segment, the segment-data classification characterizing the data stored in the respective segment; and a read access in which data corresponding to a predetermined data classification are read from the external memory.

Abstract: A storage system such as a storage array in a data center calculates per-application power utilization based on monitored IOs. IOs generated by applications that are tolerant of rescheduling may be rescheduled to a time when power is less costly or more available. Storage array power consumption is reduced if all services host applications can tolerate greater IO latency without service level violations. Server power consumption is reduced if all services host applications can tolerate greater IO latency without service level violations. Power consumption by the servers, storage array, or both is reduced if power consumption reaches a predetermined level relative to available power.

Abstract: Methods, systems, and devices for memory bus drive defect detection and related operations are described. A controller coupled with a memory array may receive a command for data. The memory array may include one or more pins for communicating data to and from the memory array, in response to the command. The controller may transmit to the memory array, over a bus that is coupled with the controller and the pins, the command. The controller may detect, based at least in part on a resistor coupled with the bus and a power supply of the memory array, that the bus is operating in a first state after transmitting the command. The first state may comprise a voltage that is relatively higher than a voltage of the second state. The controller may determine a defect associated with the bus or the pin based on detecting the bus in the first state.

Abstract: One embodiment can provide a node controller in a multiprocessor system. The node controller can include a processor interface to interface with a processor, a memory interface to interface with a fabric-attached memory, a node-controller interface to interface with a remote node controller, and a cache-coherence logic to operate in a first mode or a second mode. The cache-coherence logic manages cache coherence for a local memory of the processor coupled to the processor interface when operating in the first mode, and the cache-coherence logic manages cache coherence for the fabric-attached memory coupled to the memory interface when operating in the second mode.