Abstract: Systems and methods are disclosed herein to provide improved I/O techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a reference circuit adapted to receive a first reference signal and provide a second plurality of reference signals based on the first reference signal, with the reference circuit providing default voltage levels for the second plurality of reference signals if a first control signal is asserted. An input/output circuit, coupled to the reference circuit and to an output driver, receives the second plurality of reference signals to control the output driver to provide an output signal, with the output driver operated with the default voltage levels if the first control signal is asserted.

Abstract: Logic activation circuit for switching a logic circuit having at least one supply voltage line on or off, said logic activation circuit having: (a) at least one voltage supply switching device for connecting a supply voltage to a supply voltage line of the logic circuit in a manner dependent on a changeover control signal that is applied to a control terminal of the voltage supply switching device; and having (b) a charge equalization switching device which, in a manner dependent on a control switching pulse, connects the supply voltage line of the logic circuit to the control terminal of the voltage supply switching device for the duration of the control switching pulse so that charge equalization is effected between the supply voltage line and the control terminal of the voltage supply switching device in order to generate the changeover control signal.

Abstract: Techniques are provided for controlling on-chip termination (OCT) impedance using OCT calibration blocks that serially transmit OCT control signals to input/output (IO) blocks. The OCT control signals are serially transmitted through a shared conductor. An OCT calibration block can transmit OCT control signals to one or multiple IO blocks. The IO blocks can be programmed to select OCT control signals from one of the calibration blocks. Enable signals enable one or more of the IO blocks to receive the selected OCT control signals. The OCT control signals are used to control the on-chip termination impedance at one or more IO buffers.

Abstract: A circuit for calibrating a resistance value on an integrated circuit includes a resistor network, a reference voltage generator, a comparator, a servo loop, and a shift register. The resistor network includes a plurality of resistor and switch pairs in parallel. The resistor network further includes a servo resistor in series with a servo resistor switch such that the servo resistor and servo resistor switch are in parallel with the plurality of resistor and switch pairs. The servo loop generates a shift register gating signal and includes a current sample register for storing a current comparator output data value and a previous sample register for storing a previous comparator output data value. The shift register, upon receipt of a shift register gating signal at a first state, inputs the current comparator output data value to shift data bits through the shift register.

Abstract: A receiver circuit for receiving and forwarding data signals comprises at least one first and one second input to be used to inject an external digital data signal and a reference signal into the receiver circuit, a multistage input amplifier circuit which comprises a first amplifier stage and a second amplifier stage connected downstream of the first amplifier stage, and a device for actively setting a first operating point of the multistage input amplifier circuit. The multistage input circuit provides the external digital data signal in amplified form at an output and the device generates a bias potential for driving the input multistage amplifier circuit on the basis of the circuit topography of the multistage input amplifier circuit. The bias potential is used to set a second operating point of the first amplifier stage in such a manner that its output signal is within a prescribed third operating point of the second amplifier stage.

Abstract: A scannable latch incorporates a logic front end that has at least one dynamic logic gate that has a logic tree that perform the normal Boolean logic operation. The dynamic logic gate is combined a scan pull-down logic tree that is coupled to a scan hold latch output and to the dynamic node of the dynamic logic gate. A scan clock and a normal clock determine whether the logic circuitry is in the normal logic mode or in the scan test mode. A static output latch has at least one input that is responsive logic state of a dynamic node. The evaluated state of the dynamic node is set by either the logic tree of the dynamic logic gate or the scan pull-down logic tree of the scan circuitry in response to the logic state of the scan clock or the normal clock.

Abstract: An apparatus for controlling an on die termination (ODT) includes a counting unit for receiving an external clock signal and a delay locked loop (DLL) clock signal, and counting the toggle number of each of external clock signal and the DLL clock signal from a preset number; a comparing control unit for comparing the counted toggle number of the external clock signal with that of the DLL clock signal in response to an ODT command signal, and outputting an ODT enable signal for controlling the ODT based on the compared result.

Abstract: A logic device with low electromagnetic interference. The logic device includes a digital logic gate, a voltage-limited circuit and a current-limited circuit. The digital logic gate provides a corresponding digital logic function. The voltage-limited circuit is connected to the digital logic gate in order to provide a fixed voltage to the digital logic gate to thus reduce an output voltage swing of the digital logic gate. The current-limited circuit is connected to the digital logic gate in order to provide a fixed current to the digital logic gate to thus reduce a transient current of the digital logic gate. Accordingly, an electromagnetic interface (EMI) caused by switching of the digital logic gate is reduced with the reduced output voltage swing and transient current.

Abstract: A level shifter circuit for shifting a voltage level of a logic signal from a first voltage to a second voltage includes an input stage operating in a domain of a first voltage supply that receives an input signal. The input stage includes a first inverter receiving the input signal and providing a first inverted signal. An output voltage level shifting stage operating in a domain of a second voltage supply is coupled to the input stage and providing an output signal having a voltage level corresponding to the second voltage supply domain and a logic value corresponding to the input signal. The level shifter circuit enables voltage level shifting a logic signal from a high to a low operating voltage, or from a low to a high operating voltage. The level shifter circuit enables high frequency operation, providing both fast switching and low capacitance.

Abstract: A chip-to-chip digital transmission circuit includes a differential driver portion, a pair of differential signal transmission lines connected to the driver portion, and a receiver portion connected to the transmission lines, an output node of which reproduces a digital bit stream originally presented to a driver side input node, wherein the transmission lines carry both transmitted signal information and DC power for the receiver portion. The driver portion is configured to adjust both the transmitted signal magnitude and the DC power delivered to the receiver portion.

Abstract: A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.