Abstract: A mobile terminal and antenna including a case configured to include a circuit board and an antenna disposed inside the case. The antenna including an antenna pattern formed on a substrate, a feed unit having a first end connected to the antenna pattern and a second end connected to the circuit board. The feed unit is configured to supply an electrical signal to the antenna pattern, and an Electromagnetic Interference (EMI) attenuation unit is disposed in a location corresponding to the feed unit and configured to attenuate the EMI generated by the feed unit.

Abstract: Carrier with solid antenna structure comprises a substrate and at least one solid antenna structure. The substrate has an upper surface, a lower surface, at least one first slot communicating with the upper surface and the lower surface and at least one second slot communicating with the upper surface and the lower surface. The solid antenna structure has a dielectric block formed between the first slot and the second slot and a radiation conductor, in which the dielectric block encloses the radiation conductor. In this invention, the solid antenna structure is used to enable the carrier to be applied to higher power transmission. Additionally, by setting the material of the dielectric block and optimizing the size of the radiation conductor, the carrier can be applied to multi-band.

Abstract: An improved interconnect structure in programmable devices gives a new dimension to the routing architecture, where architecture is divided into various domains. It includes at least one set of input lines, each set having predetermined number of input lines; an equal number of sets of routing lines, each set of routing lines being connected to a corresponding set of input lines using a switch box; thereby forming domain based routing structures, each domain being disjoint with the other domain. Segregating FPGA routing resources into various independent routing domains is done; each domain providing connectivity to route a signal to a set of sinks.

Abstract: An antenna device suitable for short distance wireless communication is provided which can have a good symmetry of directional characteristics and increase a gain at both end sides in a longitudinal direction of a ground pattern. An antenna device is formed by patterning a metal conductor on a printed substrate. The antenna device is provided with a ground pattern of a rectangular shape, a power feed element arranged adjacent to one short side portion of the ground pattern, a correction pattern that projects from the short side portion and is located lateral to the power feed element, and a parasitic radiation element extending along the short side portion at a separation position facing the short side portion of the ground pattern through the power feed element and the correction pattern. An electrical length of the parasitic radiation element is set to be approximately ½ of a resonant length. When power is feed, the power feed element is excited to radiate electric waves.

Abstract: A buffer circuit uses (e.g., active) inductors for driving capacitive loads. In one embodiment, the buffer circuit has one or more stages, each stage having one CMOS inverter. Each CMOS inverter has one NMOS transistor and one PMOS transistor and is coupled to a stage input and a stage output. Additionally, at least one stage of the buffer circuit has two inductors, each coupled between a different voltage reference for the buffer circuit and the stage output. One inductor has a PMOS transistor coupled to the gate of an NMOS transistor and the other inductor has an NMOS transistor coupled to the gate of a PMOS transistor. When driving capacitive loads, the inductors partially tune out the apparent load capacitance CL, thereby improving the charging capabilities of inverter and enabling quicker charge and discharge times. Furthermore, partially tuning out apparent load capacitance facilitates the driving of larger capacitive loads.

Abstract: A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

Abstract: A programmable logic device can include a logic core in low power mode, a source input/output (I/O) bank including at least one source I/O pin, wherein the source I/O bank operates in normal operating mode, and a destination I/O bank including at least one destination I/O pin, wherein the destination I/O bank operates in normal operating mode. The programmable logic device also can include a bypass routing bus coupled to the source I/O bank and the destination I/O bank, wherein the bypass routing bus detects an I/O signal from the source I/O pin, responsively generates a bypass signal that is provided to the destination I/O bank and, responsive to the bypass signal, generates an output bypass signal on the destination I/O pin.

Abstract: A programmable logic device (“PLD”) architecture includes logic elements (“LEs”) grouped together in clusters called logic array blocks (LABs”). To save area, local feedback resources (for feeding outputs of the LEs in a LAB back to inputs of LEs in the LAB) are reduced or eliminated as compared to in the prior art. Because all (or at least more) of any LE-output-to-LE-input connections of LEs that are working together in a LAB must be routed through the general-purpose input routing resources of the LAB, it is important to conserve those resources. This is accomplished, for example, by giving greater importance to finding logic functions that have common inputs when deciding what logic functions to implement together in a LAB.

Abstract: A state machine is provided with outputs that have programmable delays that enable the state machine to be compatible with a number of different devices. The state machine uses shift register look up tables (SRLs) to provide variable output delays. The state machine can be provided in the BRAM of an FPGA, and can be used to provide control logic in a multi-port memory controller (MPMC). The MPMC with such a state machine can then connect to multiple different types of memory devices either simultaneously or separately.

Abstract: A differential level shifter employs a variable current mirror to maintain a reference voltage at one output while the other output follows a differential input. Resistor networks allow postproduction trimming of load resistors and the current mirror, resulting in a precise and accurate output of the differential signal. An active cascode circuit enhances current mirror balance and high frequency operation.

Abstract: A voltage-controlled oscillator includes: a bias voltage generator operating to generate first and second bias voltages in response to a control signal; a voltage-controlled oscillation circuit connected to a control node and configured to generate oscillation signals in response to an input voltage; a selection signal generator operating to generate a selection signal in response each to the oscillation signals; and a selection circuit operating to select one of the first and second bias voltages in response to the selection signal and outputting the selected bias voltage to the control node.

Abstract: A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.

Abstract: A pulse generation section generates a pulse which is at H-level for the predetermined period of time from the timing of the input signal DATA changing to L-level. A main output section outputs a signal of L-level with transistors P1, N1, and N2 turned ON, while the pulse generation section outputs a pulse. When the pulse falls, the transistors P1 and N1 are turned OFF, and a potential of an output node is held at L-level by resistors of a L-level holding section.

Abstract: The present invention provides a method and mechanism for adapting a single phase-locked loop (PLL) for a wider range of frequencies than has been possible with prior art solutions. An analog comparator circuit that senses the output of a charge pump and provides a signal to a digital control circuit to choose a suitable load circuit for the PLL voltage controlled oscillator (VCO). The analog comparator with the digital control circuit changes the VCO loads to select the best VCO range to achieve the incoming signal frequency lock. A single PLL with the VCO load selection method disclosed, with use of built-in hysteresis, in addition to the phase and frequency feedback of the prior art, allows multiple overlapping frequency ranges to be covered in a stable fashion. This enables frequency locking of the PLL over a wide range of frequencies with a small die size and low power consumption.

Abstract: A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.

Abstract: High-speed serial interface (“HSSI”) transceiver circuitry (e.g., on a programmable logic device (“PLD”) integrated circuit) includes input buffer circuitry with adaptive equalization capability. The transceiver circuitry also includes an output driver, which may include pre-emphasis capability (preferably controllably settable). Selectively usable loop-back circuitry is provided for allowing the output signal of the input buffer to be applied substantially directly to the output driver. The loop-back circuitry may include a loop-back driver, which may be turned on substantially only when needed for loop-back operations.

Abstract: An embodiment of the invention relates to a T-switch for connecting first, second and third lines and comprising an input section in turn including first, second and third input pass transistors, each connecting a respective line with a first internal node of the T-switch, an output section in turn including first, second and third output pass transistors, each connecting a respective line with a second internal node of the T-switch, and a single buffer stage connected to a first and a second voltage reference and inserted between the first and second internal node.

Abstract: Techniques are provided for controlling an on-chip termination (OCT) in an output driver. The OCT control circuit calibrates the effective resistance of transistors in the output driver to match an external resistor using a feedback loop. The feedback loop monitors the output voltage and generates an analog calibration signal that varies the output impedance of a selected group of the output transistors that are enabled to drive the output terminal. Digital signals under the control of the user select the number of output transistors to be enabled based on the output driver requirements of the circuit. The analog calibration signal varies the signal level driving the selected output transistors to modify the effective output impedance of the circuit for better termination matching.

Abstract: The terminating impedance of a networked device in a wired communication channel is controlled to avoid an impedance discontinuity when power is applied and removed from the node or other event occurs that would change the impedance of the signal interface. When the node transmits or receives signals using the communication channel, the transmit or receive device presents a matched termination to the channel. When power is removed or the device is reset, the transmit and receive circuitry is not operational and the matched impedance is therefore maintained by a separate device. The impedance may be varied slowly from a match to a high impedance to allow other devices in the network to adapt to the change in multipath environment that results from the impedance change. Alternatively, the signal interface can be switched to a passive static impedance that is maintained while power is off or the disrupting event occurs.

Abstract: An integrated circuit is provided with adjustable transistor body bias circuitry and adjustable power supply circuitry. The adjustable circuitry may be used to selectively apply body bias voltages and power supply voltages to blocks of programmable logic, memory blocks, and other circuit blocks on the integrated circuit. The body bias voltages and power supply voltages may be identified by computer aided design tools. The body bias voltages may be used to reduce leakage currents and power consumption when high speed circuit block operation is not required. Reduced power supply voltages may also be used to reduce power consumption when high speed circuit block operation is not required. To ensure optimum switching speeds, circuit blocks for which high-speed performance is critical can be provided with minimal body bias voltage or no body bias and can be provided with maximum power supply levels.