Abstract: Systems and methods are disclosed herein to provide improved security key techniques for programmable logic devices. For example, in accordance with an embodiment of the present invention, a method of providing data security for a programmable logic device (PLD) includes programming a plurality of programmable fuses that stores a security key comprising a plurality of data bit values, wherein each data bit value is associated with a respective subset of at least three of the fuses. The security key is retrieved from the fuses using the data bit values stored by each subset of the fuses. An encrypted configuration data bitstream is decrypted using the retrieved security key to obtain an original configuration data bitstream to configure the PLD.

Abstract: A voltage supply control circuit is arranged between a true ground voltage and a pseudo ground line. In an active mode, first and second control signals are at the “H” and “L” levels, respectively. In response to this, a first switch is turned on so that a first node is electrically coupled to a power supply voltage, and attains the “H” level. Further, a second switch is turned on to couple electrically the ground voltage to a second node. In a standby mode, the first and second control signals are at the “L” and “H” levels, respectively. In response to this, a third switch is turned on to couple electrically the first and second nodes together. Since the power supply voltage was electrically coupled to the first node according to the turn-on of the first switch in the active mode, the path of the control signal including the first node to the switch has accumulated charged charges.

Abstract: A programmable logic device, in accordance with an embodiment of the present invention, includes a plurality of multiplexers, having fuse input terminals and input signal terminals, and a plurality of associated fuses providing fuse signals to the fuse input terminals to control selection of the input signal terminals. The fuses in a first state select a first input signal terminal of the input signal terminals, with a first multiplexer from the plurality of multiplexers receiving a first logic level signal at the first input signal terminal and providing the first logic level signal to the first input signal terminal of a first set of the plurality of multiplexers. The fuses associated with the first set are adapted to be programmed before the fuses associated with the first multiplexer.

Abstract: A method of reducing power of a circuit is described. The method includes determining at least one unused selection input associated with stages of a multiplexer tree; pulling the at least one unused selection input to a constant value; and assigning predetermined values to unused data inputs of the multiplexer tree associated with the at least one unused selection input.

Abstract: Signals sent from one system-on-chip core become switched to a reconfigurable logic core (RLC) for observation and, perhaps, replacement with another signal. A first signal line couples together a plurality of cores. A switch, disposed between the first signal line and an input signal line of the RLC, selectively controls whether the signal gets sent to the RLC. A multiplexer, having the first signal line and an output signal line of the RLC as inputs, selectively controls whether the signal or a replacement signal becomes conveyed to another core of the system-on-chip. Observation and control configuration memory bits act as inputs in the selective control of the switch and the multiplexer. Other embodiments teach shared RLC input signal lines amongst multiple cores. The RLC may contain an inverter, a test circuit, a logic analyzer or other. Methods of observing and replacing signals are also taught.

Abstract: Systems and methods for increasing the frequency range of an output signal generated by a VCO, where one or more variable delay units are incorporated into an interpolative VCO to decrease the minimum frequency at which the VCO oscillates. In one embodiment, the VCO includes a ring of serially connected inverters, a set of bypass circuits and a set of variable delay units. The bypass circuits are coupled to the ring of serially connected inverters to bypass one or more of the serially connected inverters when enabled. Each variable delay unit delays signal transitions at the input of a corresponding one of the serially connected inverters by a variable amount. The variable delay units may be positioned in series with the ring of inverters, in parallel with the bypass paths, or in parallel with corresponding inverters in the ring of inverters.

Abstract: In data transmission apparatus, a transmission line is connected with a transmitting unit and includes a first transmission line and a second transmission line. A receiving unit is connected with the transmission line. A terminating resistance is connected between a first reception node connected with the first transmission line on a receiving unit side and a second reception node connected with the second transmission line on a receiving unit side. The transmitting unit transmits a transmission data to the receiving unit through the transmission line. The receiving unit detects a reception data corresponding to the transmission data based on an amplitude voltage as a voltage difference between the first reception node and the second reception node.

Abstract: Dynamically configurable routing logic coupled between physical I/O ports and special purpose I/O associated with functions within a panel ASIC is disclosed that provide different routing configurations between the physical I/O ports and the special purpose I/O. In one routing configuration, any special purpose output can be coupled to one or more physical I/O ports, providing flexibility to route any functional I/O to any physical I/O port. In a second routing configuration, any input signal on a physical I/O port can be coupled to one or more special purpose inputs. In a third routing configuration, the input signals on a number of physical I/O ports can be configured to independently assert a single special purpose input for interrupt triggering. The dynamically configurable nature of the routing logic allows routing to be changed on the fly.

Abstract: A programmable logic device (“PLD”) architecture includes logic elements (“LEs”) grouped together in clusters called logic array blocks (LABs”). To save area, local feedback resources (for feeding outputs of the LEs in a LAB back to inputs of LEs in the LAB) are reduced or eliminated as compared to in the prior art. Because all (or at least more) of any LE-output-to-LE-input connections of LEs that are working together in a LAB must be routed through the general-purpose input routing resources of the LAB, it is important to conserve those resources. This is accomplished, for example, by giving greater importance to finding logic functions that have common inputs when deciding what logic functions to implement together in a LAB.

Abstract: An antenna array has a ground plane, a plurality of spacers, a radiating patch array and a feeding member. The spacers are mounted on the ground plane. The radiating patch array is mounted on the spacers, is separated from the ground plane at an interval and has three pairs of radiating patches. Each radiating patch is parallel to the ground plane and has a sub radiating patch formed on and inclined away from the ground plane. The inclined sub radiating patches and the interval increase gain of the antenna array.

Abstract: First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.

Abstract: Embodiments of the present invention provide level shifter circuits capable of high frequency operations. The level shifter circuit utilizes a dynamic charge injection device, which diminishes a capacitive coupling effect between a gate and a drain of input NMOS devices, when the input signal switches from a high logic level to a low logic level. The dynamic charge injection device is incorporated at output nodes to provide initial thrust to the level shifter circuits, which triggers a positive regenerative feedback of cross-coupled pull up PMOS devices enabling a rapid transition and hence the high frequency operation.

Abstract: Systems and methods provide programmable logic block architectures and routing architectures for the programmable logic blocks. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks. A first routing circuit provides global signal routing within the programmable logic device for the corresponding programmable logic block. A first input routing circuit receives signals from the first routing circuit and routes the signals to the logic block slices within the corresponding programmable logic block.

Abstract: There is provided a differential current driving current type transmission system. The system includes a transmission line pair for transmitting a signal by a differential scheme; a transmission unit having a transmission circuit for making the transmission line pair have a current difference according to a logic value of a transmission signal and equalizing the transmission line pair at a predetermined timing, and a transmission controller for controlling the signal transmission of the transmission circuit and the equalization of the transmission line pair; and a receiving unit having an I-V converter circuit for mirroring a current difference of the transmission line pair and converting the current difference into a voltage difference, and a differential amplifier for amplifying the voltage difference of the I-V converter circuit.

Abstract: In one embodiment of the invention, a programmable level shifter can be selectively configured to operate in either a high-speed mode or a low-power mode. In both modes, the level shifter converts an input signal in one power supply domain into an output signal in another power supply domain. In the high-speed mode, p-type devices are configured as a current-mirror amplifier that provides the level shifter with relatively fast switching speed. In the low-power mode, the same p-type devices are configured as a cross-coupled latch that provides the level shifter with relatively low power consumption. Selectively enabled n-type devices provide the low-power mode with larger effective n-type devices to flip the cross-coupled latch formed by the p-type devices in the low-power mode.

Abstract: Disclosed is an I/O cell for providing an output pad with an output signal, including a first drive circuit for providing the output pad with an output signal having a drive strength which is equal to a drive strength required by a basic PMOS transistor or a basic NMOS transistor, the first drive circuit further operating as an ESD protection circuit to protect the output pad from any errant electrostatic signal input thereto; and a at least one second drive circuit connected between an output of the first drive circuit and the output pad, the second drive circuit operating as an ESD protection circuit to further protect the output pad from any errant electrostatic signal input thereto.

Abstract: An input/output (I/O) structure includes a delay element usable for the input path, the output path, or both input and output paths in a user design. In a first mode, the delay element is included in the input path. In a second mode, the delay element is included in the output path. In a third mode, the I/O structure includes the delay in both outgoing signal paths and incoming signal paths, e.g., by utilizing an output tristate signal to control the direction of the delay line. When the output buffer is driving, the delay is inserted in the output path. When the output buffer is tristated, the delay is inserted in the input path. Thus, a single delay element is dynamically shared by both input and output signals that use the same I/O pad. In an optional fourth mode, the delay element is bypassed by both input and output signals.

Abstract: A low power logic output buffer includes first and second logic gates, each having an input and an output. The input of the first logic gate receives a first logic signal, and the input of the second logic gate receives a second logic signal. The buffer includes first, second, third and fourth n-type metal oxide semiconductor (NMOS). The buffer also includes first and second bias switching NMOS. The first bias switching NMOS is coupled between the source of the third NMOS and ground, and the gate of the first bias switching NMOS is coupled to the output of the first logic gate. The second bias switching NMOS is electrically coupled between the source of the fourth NMOS and ground, and the gate of the second bias switching NMOS is coupled to the output of the second logic gate.

Abstract: A high speed logic signal level shifter is comprised of: a logic signal buffer for receiving logic signal information and having true and complement state differential outputs; a binary flip-flop circuit with set and reset inputs; a first coupling capacitor connected from the true buffer output to the set input of the binary flip-flop circuit; and a second coupling capacitor connected from the complement buffer output to the reset input of the binary flip-flop circuit. The high speed logic signal level shifter transfers a fast logic signal across a high voltage difference by making use of rapid voltage changes transmitted through small capacitors. The signal changes carried by the capacitors are about 10 times faster than any expected voltage transient on VPP or VNN. Furthermore, the differential coupling circuit is used to provide enhanced protection against undesired circuit switching during supply voltage changes.

Abstract: A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether there is sufficient internal clocking available to operate the ODT portion in the output driver in the synchronous mode of operation or to switch the operation to the asynchronous mode. The clock-sufficiency based determination of internal ODT mode of operation (synchronous vs. asynchronous) avoids utilization of complex and inflexible clock processing logic in an ODT control unit in the output driver. This enables the actual clocking to the ODT circuitry to be changed during various device operational modes (e.g., active, power down, etc.) without re-designing the ODT control logic for each of those modes. The simplicity and flexibility of the ODT mode detector design allows for efficient use of chip real estate without affecting the signal transfer speed of the output driver in the electronic device.