Abstract: A transmission circuit and related method are disclosed. A transmitter in the transmission circuit has CMOS transistors as driving units for responding an input signal to drive an output signal at an output node, and each driving unit has a corresponding charge unit formed by a capacitor-connected MOS of a same type as that of the corresponding driving unit. Each charge unit is controlled by an auxiliary signal inverse to the input signal. When a level transition occurs in the input signal, the charge unit can compensate charge injection and clock feed-through caused by the driving unit at the output node, and form peaks for pre-emphasis. In this way, a better transmission property can be realized by using a simpler and low-power circuit design.

Abstract: In resonant elements 102 to 105 constituting a resonant circuit, an uncontrolled cross coupling which exists between two resonant elements is controlled by using a coupling element 106 which is newly arranged between the resonant elements, whereby it is possible to create a state where two resonant elements are not coupled with each other or a state where the amount of the coupling is reduced, which states are difficult to be realized on a plane. As a result, it is possible to improve characteristics of a planar filter.

Abstract: First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.

Abstract: Two or more buffers may configured and arranged such that a quiescent current that flows through and biases a first buffer also flows through and biases a second buffer. The first and second buffers may, for example, be source followers used as reference buffers that drive inputs of a switched-capacitor circuit.

Abstract: The apparatus for on-die termination of a semiconductor memory includes a first ODT (On-Die Termination) voltage generating unit that outputs a first line voltage by calibrating an input voltage with a resistance ratio according to a first code having at least two bits; a first code calibrating unit that counts the first code according to the result of a comparison between the first line voltage and a reference voltage, stops the code count when the first code reaches a maximum value or a minimum value, and stores a code value based on a final count; a second ODT voltage generating unit that outputs a second line voltage by calibrating an input voltage with a resistance ratio according to the first code and a second code having at least two bits; and a second code calibrating unit that counts the second code according to the result of a comparison between the second line voltage and the reference voltage, stops the code count when the second code reaches the maximum value or the minimum value, and stores a co

Abstract: An impedance matching circuit performs a ZQ calibration for a test on a wafer process of a semiconductor memory device. The impedance matching circuit of the semiconductor memory device includes a first pull-down resistance unit, a first pull-up resistance unit, a second pull-up resistance unit and a second pull-down resistance unit. The first pull-down resistance unit supplies a ground voltage to a first node in response to a calibration test signal. The first pull-up resistance unit calibrates its resistance to that of the first pull-down resistance unit to thereby generate a pull-up calibration code. The second pull-up resistance unit supplies a supply voltage to a second node in response to the pull-up calibration code. The second pull-down resistance unit calibrates its resistance to that of the second pull-up resistance unit to thereby generate a pull-down calibration code.

Abstract: A semiconductor integrated circuit includes an ODT signal generator that receives an ODT command signal, an ODT reset signal, and an ODT calibration end signal to generate an ODT control signal according to the phase of the ODT calibration end signal, and an ODT resistance adjusting unit that is to perform an on-die termination operation in response to the ODT control signal.

Abstract: A level shift circuit insusceptible to mistaken operations at the time of disengagement of a standby state is disclosed. The level shift circuit includes a level converter circuit 5, a barrier gate circuit 2 and a holding circuit (MMP1, MMP2). The level converter circuit converts a signal level of a circuit operating in a VDD1 system to a signal level of a VDD2 system. The barrier gate circuit is responsive to a standby signal (STBY) to fix input signals (AB, AAB) of the level converter circuit 5 at a LOW level. The holding circuit holds an output of the level converter circuit 5 at a constant voltage when the input signals (AB, AAB) are at the LOW level (FIG. 1).

Abstract: A multiband antenna with the broadband function has a radiator, a feed cable, a first extension conductor, and a second extension conductor. The radiator has a microwave substrate, a coupling conductor, a first conductor, a second conductor, a third conductor, and a connecting conductor. The coupling conductor is connected with a positive signal wire of the feed cable. The third conductor is connected with a negative signal of the feed cable for transmitting electrical signals. The radiator generates the multiband mode of the antenna. By connecting the first extension conductor and the second extension conductor with the radiator, the surface current distribution and impedance variation of the antenna can be effectively adjusted to achieve the broadband effect.

Abstract: A semiconductor device according to the present invention comprises a first semiconductor integrated circuit 11 having a predetermined function, the first semiconductor integrated circuit outputting a required output signal, a second semiconductor integrated circuit 12 in which a plurality of MOS elements (PMOS transistor or NMOS transistor) for independently switching to and from a conducted state and a non-conducted state in accordance with a plurality of gate signals each having a different timing is provided and the plurality of MOS elements is connected in parallel to an output or an input of the first semiconductor integrated circuit, and a pulse generating circuit 13 for generating and outputting the plurality of gate signals ?i (i=1, 2, 3) each having a different timing with respect to the plurality of MOS elements in the second semiconductor integrated circuit.

Abstract: A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.

Abstract: An apparatus for providing oscillator frequency stability is disclosed. The apparatus includes an internally ovenized oscillator module having an oscillator and an inner heater to maintain the oscillator at a first temperature during operation. The apparatus also includes a thermally conductive cover for forming a first compartment to contain the internally ovenized oscillator module along with multiple heaters. The heaters are in thermal communication with the thermally conductive cover and the substrate to form an oven to keep the internally ovenized oscillator module at a stable second temperature during operation. In addition, the apparatus includes a thermally insulative cover for forming a second compartment to contain the first compartment.

Abstract: An input buffer for an Ultradeep Sub Micron (UDSM) process which allows the UDSM process to interface with a 3V input. The input voltage is applied to a degenerated transistor which forms part of the input buffer. The input buffer effectively drops the input voltage to a voltage suitable for use by the core of the UDSM process.

Abstract: Apparatuses and methods are provided for a self-timed dynamic sense amplifier flop circuit, wherein a pulse generating circuit may be adapted to generate at least a first logic signal based, at least in part, on a first evaluation node signal, and a discharge path circuit comprising at least a first transistor within a first stack of transistors may be operatively responsive to the first timing signal.

Abstract: In one embodiment, a multiple band oscillator system is disclosed which comprises a first oscillator having a first input, a resonating element, a first output, and a second output. In addition, the multiple band oscillator system also comprises a second oscillator having a second input, a third output, and a fourth output. The first oscillator has a first oscillator frequency and the second oscillator has a and second oscillator frequency. The multiple band oscillator system also contains a tuning capacitive element coupled to the first and second oscillators for determining the second oscillator frequency, and the first oscillator and the second oscillators are both capable of operating the resonating element.

Abstract: A divider control circuit includes a first and a second delta sigma modulator configured to generate a divider control signal for a fractional-N divider and a fractional signal indicative of a phase error in the divider output. The fractional signal is supplied for control of an interpolator circuit. The divider control circuit may be implemented as a look-ahead circuit where two or more divider control signals and fractional signals are generated during a single cycle to allow the divider control circuit to be run at a reduced clock rate.

Abstract: A Programmable Logic Device (PLD) is provided with configuration memory cells displaying a superior soft error immunity by combating single event upsets (SEUs) as the configuration memory cells are regularly refreshed from non-volatile storage depending on the rate SEUs may occur. Circuitry on the PLD uses a programmable timer to set a refresh rate for the configuration memory cells. Because an SEU which erases the state of a small sized memory cell due to collisions with cosmic particles may take some time to cause a functional failure, periodic refreshing will prevent the functional failure. The configuration cells can be DRAM cells which occupy significantly less space than the SRAM cells. Refresh circuitry typically provided for DRAM cells is reduced by using the programming circuitry of the PLD. Data in the configuration cells of the PLD are reloaded from either external or internal soft-error immune non-volatile memory.

Abstract: Low voltage swing techniques are provided for simultaneously reducing the active and standby mode power consumption and enhancing the noise immunity in domino logic circuits. One or both the upper and lower boundaries of the voltage swing at the dynamic node may be different from the upper and lower boundaries of the voltage swing at the output node. Further, the domino logic circuit may use dual Vt thereby reducing the short-circuit current during operation. Meanwhile, full voltage swing signals may be maintained at the inputs and outputs for high speed operation. The low swing circuit techniques are provided that modify the output voltage swing of a domino gate, thereby reducing the active mode power consumption.

Abstract: A method of verifying configuration data to be loaded into a device having programmable logic is described. The method comprising the steps of validating a configuration bitstream to be loaded into the device having programmable logic; storing a validation indicator with the configuration bitstream in a non-volatile memory device; and configuring the programmable logic according to the configuration bitstream if the validation indicator indicates that valid data is stored in the non-volatile memory device. A system for verifying configuration data to be loaded into a device having programmable logic is also described.

Abstract: In one embodiment, a voltage-controlled oscillator (VCO) is provided that includes: a plurality of differential inverter stages coupled to form a loop, each differential inverter stage having including a switched capacitor circuit configured to control a signal delay through the differential inverter stage responsive to a control circuit, whereby an output frequency for the VCO is inherently compensated against changes in semiconductor process variations and thermal variations.