Patents Examined by Christy L. Novacek
  • Patent number: 8017466
    Abstract: In a semiconductor substrate on which are formed an N-type MOS transistor and a P-type MOS transistor, the gate electrode of the N-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the gate electrode of the P-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the concentration of carbon contained in the former tungsten film is less than the concentration of carbon contained in the latter tungsten film.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: September 13, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuaki Nakajima, Kyoichi Suguro
  • Patent number: 7999268
    Abstract: The method described herein enables the introduction of external impurities into Silicon Carbide (SiC) to be conducted at a temperature between 1150-1400° C. Advantages include: a) low temperature diffusion procedure with greater control of the doping process, b) prevent roughness of SiC surface, c) less surface defects and d) better device performance and higher yield. The method described herein involves depositing a ceramic layer that contains the desired impurity and a certain element such as oxygen (in the form of oxide), or other elements/compounds that draw out the silicon and carbon atoms from the surface region of the SiC leaving behind carbon and silicon vacancies which then allow the external impurity to diffuse into the SiC more easily. In another embodiment, the deposited layer also has carbon atoms that discourage carbon from escaping from the SiC, thus generating a surface region of excess carbon in addition to the silicon vacancies.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: August 16, 2011
    Assignee: Auburn University
    Inventors: Chin-Che Tin, Adetayo Victor Adedeji, Ilkham Gafurovich Atabayev, Bakhtiyar Gafurovich Atabaev, Tojiddin Mutalovich Saliev, Erkin Nurovich Bakhranov, Mingyu Li, Balapuwaduge Suwan Pathum Mendis, Ayayi Claude Ahyi
  • Patent number: 7989912
    Abstract: The semiconductor device includes a lower device isolation structure formed in a semiconductor substrate to define an active region. The lower device isolation structure has a first compressive stress. An upper device isolation structure is disposed over the lower device isolation structure. The upper device isolation structure has a second compressive stress greater than the first compressive stress. A gate structure is disposed over the active region between the neighboring upper device isolation structures.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: August 2, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae Yun Yl
  • Patent number: 7977225
    Abstract: In extremely scaled semiconductor devices, an asymmetric transistor configuration may be established on the basis of tilted implantation processes with increased resist height and/or tilt angles during tilted implantation processes by providing an asymmetric mask arrangement for masked transistor elements. For this purpose, the implantation mask may be shifted by an appropriate amount so as to enhance the overall blocking effect for the masked transistors while reducing any shadowing effect of the implantation masks for the non-masked transistors. The shift of the implantation masks may be accomplished by performing the automatic alignment procedure on the basis of “shifted” target values or by providing asymmetrically arranged photolithography masks.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: July 12, 2011
    Assignee: Globalfoundries Inc.
    Inventors: Andre Poock, Jan Hoentschel
  • Patent number: 7977794
    Abstract: A method of forming an aluminum line of a semiconductor device where first A metal thin layer, a first aluminum layer, and a first B metal thin layer are sequentially applied on an interlayer insulating layer. A photolithography process is performed to form a metal line pattern, and etching is performed thereon. An intermetallic dielectric layer is applied on the metal line pattern. The first B metal thin layer is removed by a chemical mechanical planarization process to form a first stage metal line. A second aluminum layer and a second metal thin layer are sequentially applied. Photoresist is applied, a photolithography process is performed to form a metal line pattern, and etching is performed to form a second stage metal line. An intermetallic dielectric layer is applied on the second stage metal line. A chemical mechanical planarization process is performed on the second intermetallic dielectric layer.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: July 12, 2011
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jae Won Han
  • Patent number: 7973341
    Abstract: A method for manufacturing a fuse of a semiconductor device comprises forming an island-type metal fuse in a region where a laser is irradiated, so that laser energy may not be dispersed in a fuse blowing process, thereby improving repair efficiency.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: July 5, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyung Jin Park, Won Ho Shin
  • Patent number: 7968506
    Abstract: After trench line pattern openings and via pattern openings are formed in a inter-metal dielectric insulation layer of a semiconductor wafer using trench-first dual damascene process, the wafer is wet cleaned in a single step wet clean process using a novel wet clean solvent composition. The wet clean solvent effectively cleans the dry etch residue from the plasma etching of the dual damascene openings, etches back the TiN hard mask layer along the dual damascene openings and forms a recessed surface at the conductor metal from layer below exposed at the bottom of the via openings of the dual damascene openings.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: June 28, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Li Chou, Syun-Ming Jang, Jyu-Horng Shieh, Chih-Yuan Ting
  • Patent number: 7960193
    Abstract: A dual panel-type organic electroluminescent display device includes first and second substrates facing and spaced apart from each other, an array element layer disposed along an inner surface of the first substrate, the array element including a thin film transistor, a connection pattern disposed on the array element layer and electrically connected to the thin film transistor, a color filter layer disposed along an inner surface of the second substrate, the color filter layer including red, green, and blue color filters, an overcoat layer disposed on the color filter layer, the overcoat layer including a hygroscopic material, an organic electroluminescent diode disposed on the overcoat layer and connected to the connection pattern, the organic electroluminescent diode including a first electrode, an organic light-emitting layer, and a second electrode sequentially formed on the overcoat layer, and the organic light-emitting layer emits substantially monochromatic light, and a seal pattern along peripheral p
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: June 14, 2011
    Assignee: LG Display Co., Ltd.
    Inventor: Jae-Yong Park
  • Patent number: 7955900
    Abstract: Some embodiments of the invention include a coated thermal interface to bond a die with a heat spreader. The coated thermal interface may be used to bond the die with the heat spreader without flux. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: June 7, 2011
    Assignee: Intel Corporation
    Inventors: Susheel G. Jadhav, Carl Deppisch
  • Patent number: 7955971
    Abstract: A structure and methods of fabricating the structure. The structure comprising: a trench in a dielectric layer; an electrically conductive liner, an electrically conductive core conductor and an electrically conductive fill material filling voids between said liner and said core conductor.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: June 7, 2011
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Kaushik Chanda, Daniel Edelstein, Baozhen Li
  • Patent number: 7951694
    Abstract: A method of manufacturing a nitride semiconductor structure includes disposing a semiconductor substrate in a molecular beam epitaxy reactor; growing a wetting layer comprising AlxInyGa(1?(x+y))As(0?x+y?1) or AlxInyGa(1?(x+y))P(0?x+y?1) on the substrate; in-situ annealing the wetting layer; growing a first AlGaInN layer on the wetting layer using plasma activated nitrogen as the source of nitrogen with an additional flux of phosphorous or arsenic; and growing a second AlGaInN layer on the first AlGaInN layer using ammonia as a source of nitrogen.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: May 31, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Stewart Edward Hooper, Jonathan Heffernan
  • Patent number: 7943460
    Abstract: A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: May 17, 2011
    Assignee: International Business Machines Corporation
    Inventors: Renee T. Mo, Huiming Bu, Michael P. Chudzik, William K. Henson, Mukesh V. Khare, Vijay Narayanan
  • Patent number: 7939361
    Abstract: Gold bumps are located over electrode pads of a solid imaging device and an adhesive is formed over the gold bumps. A transparent plate is supported by the gold bumps and is made to adhere over the solid imaging device by the adhesive. The gold bumps and an electrode and wiring pattern formed over a circuit board are connected by gold wires. At this time the gold wires are approximately parallel to the circuit board near portions where the gold wires and the gold bumps are connected. As a result, it is easy to locate the transparent plate over the portions where the gold wires and the gold bumps are connected. By locating the adhesive over the portions where the gold wires and the gold bumps are connected, the solid imaging device can be made small and light. As a result, a smaller lighter semiconductor device is fabricated.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: May 10, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Toshiyuki Honda
  • Patent number: 7939365
    Abstract: A phase change memory (PCM) device, a manufacturing technique of making the PCM device, and a way of operating the PCM device is presented. The PCM device is structured to have a silicon on insulator type substrate that provides an advantage of thermally insulating the active area of the PCM device without the need for an additional insulation layer. The PCM device has a phase change resistor PCR that has one terminal connected to a word line and the other terminal connected in common to the N-terminals of two PN diodes in which the P-terminals are connected in common to the bit line. As a result, a current flowing through the phase change resistor PCR is doubled which results in doubling the cell driving capacity.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: May 10, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hee Bok Kang, Suk Kyoung Hong
  • Patent number: 7939366
    Abstract: A method of forming a phase change memory device includes forming a core pattern on a substrate, conformally forming a heat conductive layer on the substrate including the core pattern, anisotropically etching the heat conductive layer down to a top surface of the core pattern to form a heat electrode surrounding a sidewall of the core pattern, and forming a phase change memory pattern connected to a top surface of the heat electrode.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: May 10, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Jong Song, Seung-Pil Ko, Dong-Won Lim
  • Patent number: 7932148
    Abstract: This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a shielded gate trench (SGT) structure below and insulated from the trenched gate. The SGT structure is formed substantially as a round hole having a lateral expansion extended beyond the trench gate and covered by a dielectric liner layer filled with a trenched gate material. The round hole is formed by an isotropic etch at the bottom of the trenched gate and is insulated from the trenched gate by an oxide insulation layer. The round hole has a lateral expansion beyond the trench walls and the lateral expansion serves as a vertical alignment landmark for controlling the depth of the trenched gate.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: April 26, 2011
    Assignee: Alpha & Omega Semiconductor, Ltd
    Inventors: Hong Chang, Sung-Shan Tai, Tiesheng Li, Yu Wang
  • Patent number: 7923300
    Abstract: A power converter can include an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The power converter can further include a controller integrated circuit (IC) formed on a different die which can be electrically coupled to, and co-packaged with, the PowerDie. The PowerDie can be attached to a die pad of a leadframe, and the controller IC die can be attached to an active surface of the first die such that the first die is interposed between the controller IC die and the die pad.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: April 12, 2011
    Assignee: Intersil Americas Inc.
    Inventors: David B. Bell, Francois Hebert, Nikhil Kelkar
  • Patent number: 7919350
    Abstract: An image sensor is formed by providing a semiconductor substrate having first, second and third pixel regions and first and second color filters disposed on their respective pixel regions. A photoresist layer is coated over the first and second color filters and the third color pixel region. The photoresist is removed from the first and second color filters, leaving a third color filter of substantially the same height as the first and second color filters. Micro lenses may then be formed on the color filters.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: April 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hyun Cho, Jae-Ku Lee, Sun-Wook Heo
  • Patent number: 7902057
    Abstract: Fin-FET devices and methods of fabrication are disclosed. The Fin-FET devices include dual fins that may be used to provide a trench region between a source region and a drain region. In some embodiments, the dual fins may be formed by forming a trench with fin structures on opposite sides in a protruding region of a substrate. The dual fins may be useful in forming single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: March 8, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Terrence McDaniel
  • Patent number: 7892860
    Abstract: A method for forming a semiconductor laser chip is provided that can suppress layer discontinuity and simultaneously reduce fabrication variations in the light radiation angle in the horizontal direction. The method includes a step of forming, on an n-type GaAs substrate, a semiconductor element layer composed of a plurality of semiconductor layers including an etching marker layer, a step of forming, in a contact layer in the semiconductor element layer, a depressed portion having a depth not reaching the etching marker layer, and a step of forming a ridge portion by etching the semiconductor element layer by dry etching while monitoring, with laser light, the etching depth in the bottom region of the depressed portion.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: February 22, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Susumu Ohmi, Katsuhiko Kishimoto