Abstract: A GaN substrate having a large diameter of two inches or more by which a semiconductor device such as a light emitting element with improved characteristics such as luminance efficiency, an operating life and the like can be obtained at low cost industrially, a substrate having an epitaxial layer formed on the GaN substrate, a semiconductor device, and a method of manufacturing the GaN substrate are provided. A GaN substrate has a main surface and contains a low-defect crystal region and a defect concentrated region adjacent to low-defect crystal region. Low-defect crystal region and defect concentrated region extend from the main surface to a back surface positioned on the opposite side of the main surface. A plane direction [0001] is inclined in an off-angle direction with respect to a normal vector of the main surface.

Abstract: An optical waveguide apparatus having a very simple structure that can modulate a signal light guided through an optical waveguide is provided. A photoresist 13 is applied to an upper side of an SOI film 12, a photoresist mask 14 is formed, and the SOI film in a region that is not covered with the photoresist mask 14 is removed by etching to obtain an optical waveguide 15 having a single-crystal silicon core. Further, a light emitting device capable of irradiating the single-crystal silicon core with a light having a wavelength of 1.1 ?m or below is provided on a back surface side of a quartz substrate 20 to provide an optical waveguide apparatus. When the light emitting device 30 does not apply a light, the light guided through the optical waveguide 15 is guided as it is.

Abstract: A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating antimony to form a source/drain extension region in the formation of a transistor, in such a manner as to achieve high activation and avoid deactivation via subsequent exposure to high temperatures. This technique facilitates the formation of very thin source/drain regions that exhibit reduced sheet resistance while also suppressing short channel effects. Enhancements to these techniques are also suggested for more precise implantation of antimony to create a shallower source/drain extension, and to ensure formation of the source/drain extension region to underlap the gate. Also disclosed are transistors and other semiconductor components that include doped regions comprising activated antimony, such as those formed according to the disclosed methods.

Abstract: A method for fabricating a semiconductor device includes: providing a semiconductor substrate; forming a STI region on the semiconductor substrate; forming a channel region on the semiconductor substrate; implanting impurities into the STI region; and performing a thermal treatment to diffuse impurities to a side of the channel region.

Abstract: Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

Abstract: A method and apparatus are provided for manufacturing a lead frame based, over-molded semiconductor package (7) with an exposed pad or power die flag (70) having multiple integrated THT heat spreader pins (71) configured for insertion into one or more vias (77) formed in a printed circuit board (78). The through hole heat spreader pins (71) may be formed as an integral part of the exposed pad (52) or may be solidly connected with the exposed pad (62).

Abstract: A polycrystalline silicon thin film to be used in display devices, the thin film having adjacent primary grain boundaries that are not parallel to each other, wherein an area surrounded by the primary grain boundaries is larger than 1 ?m2, a fabrication method of the polycrystalline silicon thin film, and a thin film transistor fabricated using the method.

Abstract: Methods and apparatus are provided for semiconductor device (60, 95, 100, 106). The semiconductor device (60, 95, 100, 106), comprises a first region (64, 70) of a first conductivity type extending to a first surface (80), a second region (66) of a second, opposite, conductivity type forming with the first region (70) a first PN junction (65) extending to the first surface (80), a contact region (68) of the second conductivity type in the second region (66) at the first surface (80) and spaced apart from the first PN junction (65) by a first distance (LDS), and a third region (82, 96-98, 108) of the first conductivity type and of a second length (LBR), underlying the second region (66) and forming a second PN junction (63) therewith spaced apart from the first surface (80) and located closer to the first PN junction (65) than to the contact region (68). The breakdown voltage is enhanced without degrading other useful properties of the device (60, 95, 100, 106).

Abstract: A thin semiconductor layer is formed and patterned on a semiconductor substrate to form a thin semiconductor fuselink on shallow trench isolation and between an anode semiconductor region and a cathode semiconductor region. During metallization, the semiconductor fuselink is converted to a thin metal semiconductor alloy fuselink as all of the semiconductor material in the semiconductor fuselink reacts with a metal to form a metal semiconductor alloy. The inventive electrical fuse comprises the thin metal semiconductor alloy fuselink, a metal semiconductor alloy anode, and a metal semiconductor alloy cathode. The thin metal semiconductor alloy fuselink has a smaller cross-sectional area compared with prior art electrical fuses. Current density within the fuselink and the divergence of current at the interface between the fuselink and the cathode or anode comparable to prior art electrical fuses are obtained with less programming current than prior art electrical fuses.

Abstract: A semiconductor device and a method for fabricating the same that includes a drain contact that can prevent bridging between contact metals in metal contact line (M1C) processes. The method includes forming a contact hole extending through an interlayer dielectric film in a space between respective gate electrodes to expose an undercut region, filling the contact hole and the undercut region with a photosensitive material, removing the photosensitive material from the contact hole and then forming a drain contact in the contact hole.

Abstract: A method of forming a semiconductor device includes depositing a fill material (4) on a substrate portion (2) and on a dielectric layer (3) being disposed on the substrate (1) and having an opening (10) located above the substrate portion (2), removing the fill material (4) disposed above the dielectric layer (3), thereby leaving an exposed top surface (6) of the dielectric layer (3) and residual fill material (15) within the opening (10), forming a hard mask material (5) on the exposed top surface (6) of the dielectric layer (3) and on the residual fill material (15), patterning the hard mask material (5) for forming a hard mask (25) having trenches (8a, 8b) extending along a lateral direction (X) and exposing portions of the residual fill material (15) adjacent to the dielectric layer (3) and portions of the dielectric layer (3) adjacent to the residual fill material (15), anisotropically etching the dielectric layer (3), the residual fill material (15) and the substrate (1) selectively to the hard mask (5)

Abstract: A method for fabricating a capacitor includes: forming a storage node contact plug over a substrate; forming an insulation layer having an opening exposing a surface of the storage node contact plug over the storage contact plug; forming a conductive layer for a storage node over the insulation layer and the exposed surface of the storage node contact plug through two steps performed at different temperatures; performing an isolation process to isolate parts of the conductive layer; and sequentially forming a dielectric layer and a plate electrode over the isolated conductive layer.

Abstract: A microstructure includes a first structural layer and a second structural layer which faces the first structural layer with a space interposed therebetween and is partially fixed to the first structural layer. At least one of the first structural layer and the second structural layer can be displaced. Further, opposed surfaces of the first structural layer and the second structural layer are different in roughness.

Abstract: Post-laser annealing dopant deactivation is minimized by performing certain low temperature process steps prior to laser annealing.

Abstract: Hydrogen ions are implanted to a surface (main surface) of the single crystal Si substrate 10 to form the hydrogen ion implanted layer (ion-implanted damage layer) 11. As a result of the hydrogen ion implantation, the hydrogen ion implanted boundary 12 is formed. The single crystal Si substrate 10 is bonded to the quartz substrate 20 having a carbon concentration of 100 ppm or higher, and an external shock is applied near the ion-implanted damage layer 11 to delaminate the Si crystal film along the hydrogen ion implanted boundary 12 of the single crystal Si substrate 10 out of the bonded substrate. Then, the surface of the resultant silicon thin film 13 is polished to remove a damaged portion, so that an SOQ substrate can be fabricated. There can be provided an SOQ substrate highly adaptable to a semiconductor device manufacturing process.

Abstract: A semiconductor structure with dual isolation structures is disclosed. The semiconductor structure may include a protruding isolation structure in a pixel array region of a substrate and an embedded isolation structure in a peripheral device region of the same substrate. A region of the protruding isolation structure extends from an upper surface of the substrate, while another region of the protruding isolation structure may, optionally, be embedded within the substrate. The embedded isolation structure is formed within the substrate and includes an upper surface that is substantially coplanar with the upper surface of the substrate. A method of forming the semiconductor structure with dual isolation structure is also disclosed.

Abstract: A porous dielectric element is produced by forming a first dielectric and a second dielectric. The second dielectric is dispersed in the first dielectric. The second dielectric is then removed from the second dielectric by using a chemical dissolution. The removal of the second dielectric from the first dielectric leaves pores in the first dielectric. The pores, which are filled with air, improves the overall dielectric constant of the resulting dielectric element.

Abstract: It is an object of the present invention to provide a semiconductor device in which a barrier property is improved; a compact size, a thin shape, and lightweight are achieved; and flexibility is provided. By providing a stacked body including a plurality of transistors in a space between a pair of substrates, a semiconductor device is provided, in which a harmful substance is prevented from entering and a barrier property is improved. In addition, by using a pair of substrates which are thinned by performing grinding and polishing, a semiconductor device is provided, in which a compact size, a thin shape, and lightweight are achieved. Further, a semiconductor device is provided, in which flexibility is provided and a high-added value is achieved.

Abstract: A method for forming a slot contact structure for n-type transistor performance enhancement. A slot contact opening is formed to expose a contact region, and a barrier plug is disposed within a portion of the slot contact opening in order to induce a tensile stress on an adjacent channel region. The remainder of the slot contact opening is filled with a lower resistivity contact metal. Barrier plug deposition temperature can be varied in order to tune the tensile stress on the adjacent channel region.

Abstract: A method for manufacturing a fuse of a semiconductor device comprises forming an island-type metal fuse in a region where a laser is irradiated, so that laser energy may not be dispersed in a fuse blowing process, thereby improving repair efficiency.