Patents Examined by Christy Novacek
  • Patent number: 8143158
    Abstract: Embodiments of the present invention describe a method and device of preventing delamination of semiconductor layers in a semiconductor device. The semiconductor device comprises a substrate with an interlayer dielectric (ILD). A protection layer is deposited on the ILD. Next, a getter layer is formed on the protection layer to remove any native oxides on the protection layer. A capping layer is then deposited on the getter layer to prevent oxidation of the getter layer. Next, a semiconductor layer is formed on the capping layer. An oxide layer is then deposited on the semiconductor layer. Subsequently, a buffered oxide etch solution is used to remove the oxide layer. By removing the native oxides on the protection layer, the getter layer prevents the reaction between the buffered oxide etch solution and the native oxides which may cause delamination of the semiconductor layer and protection layer.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: March 27, 2012
    Assignee: Intel Corporation
    Inventor: Ajay Jain
  • Patent number: 8110874
    Abstract: A hybrid substrate circuit on a common substrate is disclosed. A first circuit formed in a first semiconductor material is isolated via a buried oxide layer from a second circuit formed in a second semiconductor material. The first and second circuits may include CMOS, HEMTs, P-HEMTs, HBTs, radio frequency circuits, MESFETs, and various pFETs and nFETs.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: February 7, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Katsura Miyashita
  • Patent number: 8101523
    Abstract: A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 ?m-10 ?m thick edge process-induced degradation layer.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: January 24, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Hidenori Mikami, Naoki Matsumoto
  • Patent number: 8093666
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a variety of electronic systems. The lanthanide yttrium aluminum oxide film may be structured as one or more monolayers. The lanthanide yttrium aluminum oxide film may be formed by atomic layer deposition.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: January 10, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8043876
    Abstract: Disclosed are a light emitting diode package and a manufacturing method thereof. According to an embodiment of the present invention, the method includes: manufacturing a package main body having a plurality of cavities, the cavities being formed in a line on one surface, through molding by putting thermoplastic polymer into a previously produced mold; forming an electrode passing through the package main body; mounting a light emitting diode chip on a basal surface of the each cavity formed in the package main body; connecting electrically the light emitting diode chip and the electrode by using a bonding means; and sealing the light emitting diode chip and the bonding means by using a molding resin.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: October 25, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hwa-Young Lee, Ho-Joon Park, Jin Cheol Kim, Sang-Jun Yoon, Geum-Hee Yun, Jun-Rok Oh
  • Patent number: 8030147
    Abstract: To provide a method for manufacturing a thin film transistor with excellent electric characteristics and high reliability and a display device including the thin film transistor. A gate insulating film is formed over a gate electrode, crystal nuclei is formed over the gate insulating film using fluorosilane and silane, and crystal growth is generated using the crystal nuclei as nuclei to form a microcrystalline semiconductor film, so that crystallinity at an interface between the gate insulating film and the microcrystalline semiconductor film is improved. Next, a thin film transistor is manufactured using the microcrystalline semiconductor film having crystallinity improved at the interface between the gate insulating film and the microcrystalline semiconductor film as a channel formation region.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: October 4, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiro Jinbo, Makoto Furuno
  • Patent number: 8017454
    Abstract: A method for forming a fuse of a semiconductor device includes performing an ion-implanting process at sides of a fuse blowing region of a metal fuse, thereby increasing the concentration of impurity ions of a thermal transmission path region. In a subsequent laser blowing process, as a result of the increased resistance of metal fuse the electric and thermal conductivity is reduced, thereby increasing the thermal condensation efficiency of the fuse blowing region and improving the efficiency of the laser blowing process.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: September 13, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Min Gu Ko
  • Patent number: 7332427
    Abstract: A method of forming an interconnection line in a semiconductor device includes forming an interlayer insulating layer on an underlying layer having a lower conductive layer, patterning the interlayer insulating layer to form an opening exposing the lower conductive layer, forming an additional material layer conformally on the underlying layer including the opening, anisotropically etching the additional material layer to form an opening spacer covering a sidewall of the opening, performing a wet etch process using the opening spacer as an etch mask, forming a conductive layer pattern in the opening, and performing a heat treatment on the opening spacer.
    Type: Grant
    Filed: December 27, 2004
    Date of Patent: February 19, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kye-Hee Yeom
  • Patent number: 7247556
    Abstract: A method of fabricating an integrated circuit (IC), during which wafer warpage is controlled by appropriately controlling intrinsic stresses in one or more service layers of the layer stack of the IC's multilevel interconnect structure. In one embodiment, each interconnect level of the multilevel interconnect structure has a dielectric layer, a conducting layer formed over the dielectric layer, and a service anti-reflective coating (ARC) layer formed over the conducting layer. Each ARC layer is formed from silicon oxynitride such that at least two ARC layers corresponding to different interconnect levels have different intrinsic stresses. The amount of intrinsic stress in each ARC layer is controlled, e.g., through the control of temperature and/or gas composition during the layer deposition.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: July 24, 2007
    Assignee: Agere Systems Inc.
    Inventors: Arun K. Nanda, Nace Rossi
  • Patent number: 7247579
    Abstract: Silicon electrode assembly decontamination cleaning methods and solutions, which control or eliminate possible chemical attacks of electrode assembly bonding materials, comprise ammonium fluoride, hydrogen peroxide, acetic acid, optionally ammonium acetate, and deionized water.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: July 24, 2007
    Assignee: Lam Research Corporation
    Inventors: Daxing Ren, Hong Shih
  • Patent number: 7241683
    Abstract: A method for forming features in an etch layer is provided. A first mask is formed over the etch layer where the first mask defines a plurality of spaces with widths. The first mask is laterally etched where the etched first mask defines a plurality of spaces with widths that are greater than the widths of the spaces of the first mask. A sidewall layer is formed over the etched first mask where the sidewall layer defines a plurality of spaces with widths that are less than the widths of the spaces defined by the etched first mask. Features are etched into the etch layer through the sidewall layer, where the features have widths that are smaller than the widths of the spaces defined by the etched first mask. The mask and sidewall layer are removed.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: July 10, 2007
    Assignee: Lam Research Corporation
    Inventors: Eric Hudson, S. M. Reza Sadjadi
  • Patent number: 7241669
    Abstract: A method of forming a scribe line having a sharp snap line entails directing a UV laser beam along a ceramic or ceramic-like substrate such that a portion of the thickness of the substrate is removed. The UV laser beam forms a scribe line in the substrate without appreciable substrate melting so that a clearly defined snap line forms a region of high stress concentration extending into the thickness of the substrate. Consequently, multiple depthwise cracks propagate into the thickness of the substrate in the region of high stress concentration in response to a breakage force applied to either side of the scribe line to effect clean fracture of the substrate into separate circuit components. The formation of this region facilitates higher precision fracture of the substrate while maintaining the integrity of the interior structure of each component during and after application of the breakage force.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: July 10, 2007
    Assignee: Electro Scientific Industries, Inc.
    Inventors: Edward J. Swenson, Yunlong Sun, Manoj Kumar Sammi, Jay Christopher Johnson, Doug Garcia, Rupendra M. Anklekar
  • Patent number: 7238624
    Abstract: The present disclosure relates generally to the manufacturing of semiconductor devices, and more particularly to semiconductor manufacturing using a vacuum chamber. In one example, a method for semiconductor manufacturing includes: providing a photoresist layer for a wafer; removing solvent residues from the photoresist layer by using a vacuum chamber; and exposing the wafer.
    Type: Grant
    Filed: March 1, 2005
    Date of Patent: July 3, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jen-Chieh Shih
  • Patent number: 7186655
    Abstract: The disclosure relates to a method for manufacturing a semiconductor device by performing a planarization process including a first CMP process using a slurry including 0.05˜0.5 wt % CeO2 or MnO2 as an abrasive and a second CMP process using a slurry including SiO2 as the other abrasive regardless of order of the processes.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: March 6, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chang Gyu Kim, Chi Hong Kim, Hi Soon Kang, Tae Won Lee, Kwang Suk Park
  • Patent number: 7183198
    Abstract: A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes that are present in the lowermost PECVD layer are closed by upper PECVD layers and therefore do not extend through all of the PECVD layers. As a result the upper surface of the uppermost PECVD layer has a lower pinhole density than the lower PECVD layer. This reduces photoresist poisoning by dopant in the amorphous carbon layer, and etching of the amorphous carbon layer by photoresist stripping chemistry.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: February 27, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pei-Yuan Gao, Lu You, Richard J. Huang
  • Patent number: 7183131
    Abstract: A process for producing a nanoelement arrangement and to a nanoelement arrangement. A first nanoelement is at least partially covered with catalyst material for catalyzing the growth of nanoelements. Furthermore, at least one second nanoelement is grown on the catalyst material. Also, a nanoelement arrangement having a first nanoelement on which at least one predetermined region is covered with catalyst material for catalyzing the growth of nanoelements, and at least one second nanoelement grown on the catalyst material.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: February 27, 2007
    Assignee: Infineon Technologies AG
    Inventors: Eugen Unger, Georg Stefan Dusberg, Andrew Graham, Maik Liebau
  • Patent number: 7183146
    Abstract: To provide a method for manufacturing a wiring, a conductive layer, a display device, and a semiconductor device, each of which can meet a large sized substrate and which is manufactured with a higher throughput by using a material efficiently, the conductive layer is formed over the substrate having an insulating surface by discharging the conductive material, and heat treatment is performed by a lamp or a laser beam over the conductive layer. Furthermore, the conductive film is formed under reduced pressure according to the present invention.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: February 27, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuko Watanabe, Yasuyuki Arai
  • Patent number: 7176563
    Abstract: Electronically grounded heat spreaders are employed in connection with the dissipation of heat, which is generated by electronic devices, such as semiconductor chips. Also provided is a novel method for the adhesive fastening of metallic heat spreaders to semiconductor chips through the combined use of electrically conductive and non-conductive adhesive materials.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: February 13, 2007
    Assignee: International Business Machine Corporation
    Inventors: Eric Duchesne, Michael A. Gaynes
  • Patent number: 7172948
    Abstract: A semiconductor process wafer having substantially co-planar active areas and a laser marked area in an adjacent inactive area and method for forming the same to eliminate a step height and improve a subsequent patterning process over the active areas wherein an inactive area trench is formed overlying the laser marked area in parallel with formation of STI trenches in the active area whereby the active areas and the inactive area are formed substantially co-planar without a step height.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: February 6, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Kun Fang, Kun-Pi Cheng, Wei-Jen Wu, Ching-Jiunn Huang, Chung-Jen Chen
  • Patent number: 7169627
    Abstract: The present invention provides a method for inspecting a connecting surface of a flip chip to solve problems that the grinding, polishing and chemical etching method is used for making a sample. The present invention utilizes ion beam etching technology for making and processing a sample of the flip chip (FC). The ion beam etching technology includes two modes: keeping the energy of ion beam and increasing the etching time; and keeping the etching time and increasing the ion beam energy. The ion beam etching technology can remove a deforming portion between the solder ball and the metal pad, which is connected thereto because of the grinding and polishing. Specially, it is easy to analyse a sample of a scanning electron microscope (SEM) which includes an intermetallic compound formed between the solder ball and the metal pad connected thereto.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: January 30, 2007
    Assignee: National Tsing Hua University
    Inventors: Jenq-Gong Duh, Shui-Jin Lu