Abstract: A plurality of bumps is formed on a substrate. At first, a hole having a bottom is formed in a sheet, and the hole is filled with a metallic paste. Then, the sheet is stacked and positioned on the substrate so that the hole of the sheet faces an electrode of the substrate. The substrate with the sheet is heated and pressurized so that the metallic paste is sintered and bonded to the electrode so as to form the bump. Then, the sheet is separated from the substrate having the bump, so that the bump is formed on the substrate. A part of each bump does not lack, and all of the bumps are formed surely. Therefore, the bump can be formed uniformly.

Abstract: A method of making an optoelectronic semiconductor package device includes attaching a conductive trace to a semiconductor chip using a transparent adhesive, wherein the chip includes an upper surface and a lower surface, and the upper surface includes a light sensitive cell and a conductive pad, then forming an encapsulant that covers the lower surface, and then forming a connection joint that contacts and electrically connects the conductive trace and the pad.

Abstract: In a method for thinning a semiconductor wafer by grinding a back surface of the semiconductor wafer in which semiconductor devices 2 are formed on its surface, the surface of the semiconductor wafer 1 is adhered to a support 4 via an adhesive layer 3, the back surface of the semiconductor wafer is ground while holding the support, and then the thinned semiconductor wafer is released from the support. Preferably, a semiconductor wafer is used as the support, a thermal release double-sided adhesive sheet is used as the adhesive layer, and they are separated by heating after grinding. Thus, there are provided a method for thinning a semiconductor wafer, which enables production of semiconductor wafers having a thickness of about 120 ?m or less without generating breakage such as cracking or chipping during the processing step and so forth as much as possible at a low cost, and a semiconductor wafer thinned further compared with conventional products in spite of a large diameter of 6 inches (150 mm) or more.

Abstract: Disclosed is a method for forming bit line and bit line contact structure. Based on a semi-finished structure with a poly plug filled in a contact window, the method of the Invention comprises steps of removing some of the oxide layer so that the plug protrudes, oxidizing the exposed region of the protruding portion of the plug, removing the oxidized portion of the plug, forming a first dielectric layer to the upper surface of the resultant structure, wherein the upper surface of the plug is exposed, forming a second dielectric layer to the upper surface of the first dielectric layer including the upper surface of the plug, forming photoresist on the second dielectric layer, then performing exposing, developing and etching to form a trench of a predetermined pattern, and filling metal into the trench to form a bit line.

Abstract: A substrate having a conductive layer is provided. A dielectric layer is then formed above the conductive layer. At least one via hole is then formed in the dielectric layer, to expose a portion of the conductive layer. The conductive layer is then covered with a gap fill polymer layer, to completely fill the via hole. A chemical mechanical polishing step is performed to remove the partial gap fill polymer layer on the outside of the via hole. An etching step, is performed to remove a portion of partial gap fill polymer layer remaining in the via hole, resulting in a partial gap fill polymer. A lithographic process is conducted to form a patterned photoresist layer over the dielectric layer. The photoresist layer has an opening that exposes the via hole and partial gap fill polymer. A portion of the dielectric layer exposed by the opening is etched away, to form a trench in the dielectric layer.

Abstract: The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. The multi-layer structure has a capping layer, that preferably comprises silicon oxide and/or silicon nitride, and which is formed over an etch resistant substrate. A patterned device layer, preferably comprising silicon nitride, is embedded in a sacrificial material, preferably comprising polysilicon, and is disposed between the etch resistant substrate and the capping layer. Access trenches or holes are formed in to capping layer and the sacrificial material are selectively etched through the access trenches, such that portions of the device layer are release from sacrificial material. The etchant preferably comprises a noble gas fluoride NGF2x (wherein Ng=Xe, Kr or Ar: and where x=1, 2 or 3). After etching that sacrificial material, the access trenches are sealed to encapsulate released portions the device layer between the etch resistant substrate and the capping layer.

Abstract: A new method and structure is provided for the polishing of the surface of a layer of low-k dielectric material. Low-k dielectric material of low density and relatively high porosity is combined with low-k dielectric material of high density and low porosity whereby the latter high density layer is, prior to polishing of the combined layers, deposited over the former low density layer. Polishing of the combined layers removes flaking of the polished low-k layers of dielectric. This method can further be extended by forming conductive interconnects through the layers of dielectric, prior to the layer of dielectric.

Abstract: An overlay mark for determining the relative position between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate is disclosed. The overlay mark includes a plurality of coarsely segmented lines that are formed by a plurality of finely segmented bars. In some cases, the coarsely segmented lines also include at least one dark field while being separated by a plurality of finely segmented bars and at least one clear field. In other cases, the coarsely segmented lines are positioned into at least two groups. The first group of coarsely segmented lines, which are separated by clear fields, are formed by a plurality of finely segmented bars. The second group of coarsely segmented lines, which are separated by dark fields, are also formed by a plurality of finely segmented bars.

Abstract: A gate structure for a semiconductor transistor is disclosed. In an exemplary embodiment, the gate structure includes a lower polysilicon region doped at a first dopant concentration and an upper polysilicon region doped at a second concentration, with the second concentration being different than the first concentration. A conductive barrier layer is disposed between the lower and the upper polysilicon regions, wherein the conductive barrier layer prevents diffusion of impurities between the lower and the upper polysilicon regions.

Abstract: A method for depositing a dielectric layer having a multi-layer structure on a substrate includes forming an oxidation barrier layer on a surface of a substrate; forming a plurality of dielectric layers on the oxidation barrier layer, wherein one of a plurality of additional oxidation barrier layers is disposed between each of the plurality of dielectric layers and an adjacent dielectric layer. Accordingly, a capacitor having low leakage current and high capacitance is obtained. In addition, a dielectric constant is controlled by adjusting a lattice constant so that a multi-layer structure of high dielectric constant is formed on a large substrate.

Abstract: A method of fabricating an SMOS integrated circuit with source and drain junctions utilizes an offset gate spacer for N-type transistors. Ions are implanted to form the source and drain regions in a strained layer. The offset spacer reduces problems associated with Arsenic (As) diffusion on strained semiconductor layers. The process can be utilized for SMOS metal oxide semiconductor field effect transistors (MOSFETs). The strained layer can be a strained silicon layer formed above a germanium layer.

Abstract: A technique for forming a high surface area electrode or storage node for a capacitor and devices formed thereby, including depositing a first layer of conductive material on a substrate, such that a discontinuous layer is formed. A second conductive material layer is deposited over the discontinuous first conductive material layer, such that the second conductive material layer grows or accumulates on the discontinuous first conductive material layer at a faster rate than on the exposed areas of the substrate in the discontinuous first conductive material layer to form a rough conductive material layer.

Abstract: Methods are provided for adjusting and controlling the stress between layers of material in a multilayer structure. A first stress is configured in a region of stress on the substrate material. A second material is then deposited over the substrate. A second stress results between the substrate and the second material such that a net stress results where the net stress is a function of said first and second stresses. As such, the first stress can be configured to achieve a predetermined, desired net stress. For example, the first stress can be configured to cancel out the second stress such that the net stress is substantially zero.

Abstract: A method of manufacturing a liquid crystal display device is intended to decrease the number of manufacturing steps. The liquid crystal display device is arranged so that in each pixel area provided on a liquid-crystal-side surface of one of a pair of substrates disposed to oppose each other with a liquid crystal interposed therebetween, a signal from a drain line is applied to a pixel electrode via a drain electrode and a source electrode which are formed in a layer overlying a semiconductor layer of a thin film transistor, by the supply of a scanning signal from a gate electrode which is positioned as an underlying layer with respect to the semiconductor layer.

Abstract: A dielectric element capable of effectively suppressing diffusion of oxygen into a region located under a lower electrode in heat treatment for sintering an oxide-based dielectric film is obtained. This dielectric element comprises a lower electrode including a first conductor film having a function of suppressing diffusion of oxygen, a first dielectric film, formed on the lower electrode, including an oxide-based dielectric film, and a first insulator film, arranged on a region other than the lower electrode, having a function of suppressing diffusion of oxygen. Thus, the first conductor film and the first insulator film function as barrier films preventing diffusion of oxygen, whereby the first conductor film effectively prevents oxygen from diffusing downward along grain boundaries of the lower electrode while the first insulator film effectively prevents oxygen from diffusing downward from the region other than the lower electrode in heat treatment for sintering the oxide-based dielectric film.

Abstract: Field effect transistor with increased charge carrier mobility due to stress in the current channel 22. The stress is in the direction of current flow (longitudinal). In PFET device, the stress is compressive; in NFET devices, the stress is tensile. The stress is created by a compressive film 34 in an area 32 under the channel. The compressive film pushes up on the channel 22, causing it to bend. In PFET devices, the compressive film is disposed under ends 31 of the channel (e.g. under the source and drain), thereby causing compression in an upper portion 22A of the channel. In NFET devices, the compressive film is disposed under a middle portion 40 of the channel (e.g. under the gate), thereby causing tension in the, upper portion of the channel. Therefore, both NFET and PFET device can be enhanced. A method for making the devices is included.

Abstract: A metal oxide high-k dielectric is deposited on a semiconductor wafer in a manner that reduces dangling bonds in the dielectric without significantly thickening interfacial oxide thickness. A metal oxide precursor and radical oxygen and/or radical nitrogen are co-flowed over the semiconductor wafer to form the high-k dielectric. The radicals bond to dangling bonds of the metal of the metal oxide during the deposition process that is performed at the regular deposition temperature of less than about 400 degrees Celsius. The radical oxygen and radical nitrogen do not require the higher temperatures generally required in an anneal in order to attach to the dangling bonds of the metal. Thus, a high temperature post deposition anneal, which tends to cause interfacial oxide growth, is not required. The dielectric is of higher quality than is typical because the dangling bonds are removed during deposition rather than after the dielectric has been deposited.

Abstract: Method and structure use support layers to assist in, for example, planarization processes to form conductive materials (e.g., a Group VIII metal) in an opening. Further, for example, such method and structure may use a Group VIII metal as an etch stop or end point for the planarization process with subsequent etching to remove undesired portions of the Group VIII metal.

Abstract: A method of fabricating a vertically profiled electrode like a T-gate 40 on a semiconductor substrate 20 is described. The method comprises providing a resist structure 34 on the substrate 20, the resist structure 34 containing at least a first resist pattern 24? arranged on the substrate 20 and having a first opening 26, the first resist being negative resist, and a second resist pattern 32 having a second opening 30 surrounding the first opening 26. The vertical profile of the gate electrode 40 is defined by the contours and the relative location of the first and the second opening 26, 30. On the resist structure 34 a metal 38 is deposited and lift-off is performed to remove the second resist 32 together with the metal 38 deposited thereon.

Abstract: Specific embodiments of the invention provide a silicon-carbide-type or silicon oxycarbide (also often called carbon-doped-oxide [CDO] or organosilicate glass) capping material and method for depositing this capping material on ELK films which are used as a dielectric material in integrated circuits. The ELK film may include any ELK film including but not limited to inorganic, organic and hybrid dielectric materials and their respective porous versions. The silicon-carbide-type material may be an amorphous silicon carbide type material such as the commercially available BLOk™ material, or a carbon-doped oxide material such as the commercially available Black Diamond™ both of which are developed by Applied Materials of Santa Clara, Calif. The amorphous silicon carbide (a-SiC) material is deposited using a plasma process in a non-oxidizing environment and the CDO-type material is deposited using an oxygen-starved plasma process.