Abstract: The invention aims at providing a dielectric film having a low dielectric constant and enhanced mechanical strength. A surfactant and an silica derivative are dissolved into a solvent at a desired mole ratio. The precursor solution is applied over the substrate, and the substrate is exposed to a silica derivative atmosphere before being sintered, thereby supplying a silica derivative. Thus, contraction of the film stemming from hydrolysis is inhibited, and a sturdy mesoporous silica thin film which takes the self-assembly of the surfactant as a mold is obtained while cavities are maintained intact without being fractured. Thus, there is formed an inorganic dielectric film which is formed on the surface of the substrate and has a cyclic porous structure including layered or columnar pores oriented so as to become parallel with the surface of the substrate.

Abstract: Disclosed is an Al alloy film for wiring, which consists of, by atom, 0.2 to 1.5% Ge and 0.2 to 2.5% Ni and the balance being essentially Al, wherein a total amount of Ge and Ni is not more than 3.0%. The invention is also directed to a sputter target material having the same chemical composition as that of the Al alloy film.

Abstract: The present infra-red light-emitting device includes a substrate with a first window layer, a silicon dioxide layer positioned on the first window layer, silicon nanocrystals distributed in the silicon dioxide layer, a second window layer, a transparent conductive layer and a first ohmic contact electrode positioned in sequence on the silicon dioxide layer, and a second ohmic contact electrode positioned on the bottom surface of the substrate. The present method forms a sub-stoichiometric silica (SiOx) layer on a substrate, wherein the numerical ratio (x) of oxygen atoms to silicon atoms is smaller than 2. A thermal treating process is then performed in a nitrogen or argon atmosphere to transform the SiOx layer into a silicon dioxide layer with a plurality of silicon nanocrystals distributed therein. The thickness of the silicon dioxide layer is between 1 and 10,000 nanometers, and the diameter of the silicon nanocrystal is between 4 and 8 nanometers.

Abstract: A bonding pad of a semiconductor device and a fabrication method thereof are disclosed. A semiconductor device having a pad formed by exposing a predetermined region of a metal line formed over a semiconductor substrate includes an alloy layer formed on the metal line exposed through the pad. The alloy layer is formed from a reaction between the metal line and a metal having a melting point less than or equal to 1000° C.

Abstract: A method of manufacturing a liquid crystal display device is intended to decrease the number of manufacturing steps. The liquid crystal display device is arranged so that in each pixel area provided on a liquid-crystal-side surface of one of a pair of substrates disposed to oppose each other with a liquid crystal interposed therebetween, a signal from a drain line is applied to a pixel electrode via a drain electrode and a source electrode which are formed in a layer overlying a semiconductor layer of a thin film transistor, by the supply of a scanning signal from a gate electrode which is positioned as an underlying layer with respect to the semiconductor layer.

Abstract: A method for cleaning and forming an oxide film on a surface, particularly a silicon surface. The surface is initially cleaned and then exposed to ozone vapor, which forms the oxide film on the surface. The method is particularly useful for forming a pre-liner oxide film on trench surfaces in the fabrication of STI (shallow trench isolation) structures.

Abstract: A semiconductor device is made by patterning a conductive layer for forming gates of transistors. The process for forming the gates has a step of patterning photoresist that overlies the conductive layer. The patterned photoresist is trimmed so that its width is reduced. Fluorine, preferably F2, is applied to the trimmed photoresist to increase its hardness and its selectivity to the conductive layer. Using the trimmed and fluorinated photoresist as a mask, the conductive layer is etched to form conductive features useful as gates. Transistors are formed in which the conductive pillars are gates. Other halogens, especially chlorine, may be substituted for the fluorine.

Abstract: Disclosed are electrolyte compositions for depositing a tin alloy on a substrate. The electrolyte compositions include tin ions, ions of one or more alloying metals, an acid, a thiourea derivative, and an additive selected from alkanol amines, polyethylene imines, alkoxylated aromatic alcohols, and combinations thereof. Also disclosed are methods of depositing a tin alloy on a substrate and methods of forming an interconnect bump on a semiconductor device.

Abstract: Disclosed is a method for pre-retaining CB opening in a DRAM manufacture process, wherein a CB opening is filed with a photo-resist layer and an LPD oxidation layer that is filled at room temperature to avoid damaging caused by conventional etching techniques. The LPD oxidation layer and the photo-resist are replaced easily by a polysilicon layer and a BPSG layer.

Abstract: A semiconductor device and fabricating method are provided, by which device drivability can be increased by forming second LDD regions after isolating first LDD regions from source/drain regions to prevent heavily doped impurities therein from diffusing into the first LDD regions and to provide stepped densities within the LDD regions. The method includes the steps of stacking oxide and conductive layers on a semiconductor substrate, forming a gate electrode by patterning the conductive layer, etching the exposed substrate to a first depth, forming a first LDD region in the etched substrate, forming a spacer on a sidewall of the gate electrode, forming a source/drain region in the substrate having the spacer, etching the substrate having the source/drain region to a second depth, and forming a second LDD region between the first LDD region and the source/drain region of the etched substrate.

Abstract: Via holes are formed in a continuous inline shadow mask production system by depositing a first conductor layer and subsequently depositing a first insulator layer over a portion of the first conductor layer. The first insulator layer is deposited in a manner to define at least one notch along its edge. The second insulator layer is then deposited on another portion of the first conductor layer in a manner whereupon the second insulator layer slightly overlaps each notch of the first insulator layer, thereby forming the one or more via holes. A conductive filler can optionally be deposited in each via hole. Lastly, a second conductive layer can be deposited over the first insulator layer, the second insulator layer and, if provided, the conductive filler.

Abstract: For patterning an IC (integrated circuit) material, a rigid organic under-layer is formed over the IC material, and the rigid organic under-layer is patterned to form a rigid organic mask structure. In addition, the rigid organic mask structure is trimmed to lower a critical dimension of the rigid organic mask structure beyond the limitations of traditional BARC mask structures. Any portion of the IC material not under the rigid organic mask structure is etched away to form an IC structure.

Abstract: The method includes forming on an underlayer wiring a first insulating film, a second insulating, and first mask forming layer; forming a first resist mask having an inverted pattern of wiring Wenches for the upper wiring; etching the first mask forming layer through the first resist mask, thereby forming in the first mask forming layer a concave part conforming to the inverted pattern of wiring tenches for the upper wiring, forming on the first mask forming layer a second mask forming layer, thereby filling the concave part with the second mask forming layer; selectively removing the second mask forming layer on the region in which the wiring trench is formed, thereby forming the second mask having the wiring trench pattern; forming on the first mask forming layer a second resist mask having an opening pattern of the via holes; etching the first mask forming layer and the second insulating film through the second resist mask, thereby forming the via holes.

Abstract: A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided. In the present invention, ions that are capable of attaching to defects within the Si-containing layer are implanted into the Si-containing layer prior to formation of metal silicide. The implanted ions stabilize the film, because the implants were found to substantially prevent agglomeration or at least delay agglomeration to much higher temperatures than in cases in which no implants were used.

Abstract: A method for fabricating a semiconductor memory device includes the consecutive steps of consecutively depositing metallic, nitride and oxide films on an underlying insulating film, patterning the nitride and oxide films to allow the oxide film to have a patterned area smaller than the patterned area of the nitride film, patterning the metallic film by using the nitride and oxide films as a mask, forming a side-wall film having a tapered mesa structure on the oxide, nitride and metallic films, embedding the side-wall oxide film by an interlayer dielectric film, and forming a contact hole in the interlayer dielectric film and the underlying oxide film while using the side-wall oxide film as an etch stopper.

Abstract: A shallow trench isolation (STI) structure and method of forming the same with reduced stress to improve charge mobility the method including providing a semiconductor substrate comprising at least one patterned hardmask layer overlying the semiconductor substrate; dry etching a trench in the semiconductor substrate according to the at least one patterned hardmask layer; forming one or more liner layers to line the trench selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride; forming one or more layers of trench filling material comprising silicon dioxide to backfill the trench; carrying out at least one thermal annealing step to relax accumulated stress in the trench filling material; carrying out at least one of a CMP and dry etch process to remove excess trench filling material above the trench level; and, removing the at least one patterned hardmask layer.

Abstract: A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.

Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a spin-on dielectric (SOD) material. A densification process is then applied, whereby the SOD material contracts and the oxidizable liner expands. Preferably, the temperature is ramped up while oxidizing during at least part of the densification process. The resulting trench has a negligible vertical wet etch rate gradient and a negligible recess at the top of the trench.

Abstract: The surface of a semiconductor material, e.g., gallium arsenide, is passivated by irradiating the surface with ultra-short laser pulses, until a stable passive surface is achieved. The passive surface so prepared is devoid of a superficial oxide layer.

Abstract: Method and structure use support layers to assist in planarization processes to form conductive materials (e.g., a Group VIII metal) in an opening. Further, such method and structure may use a Group VIII metal as an etch stop or end point for the planarization process with subsequent etching to remove undesired portions of the Group VIII metal. One exemplary method of providing a conductive material in an opening includes providing a substrate assembly having at least one surface and providing an opening defined through the surface of the substrate assembly. The opening is defined by at least one surface. At least one conductive material (e.g., at least one Group VIII metal such platinum and/or rhodium) is formed within the opening on the at least one surface defining the opening and on at least a portion of the substrate assembly surface. A support film (e.g., an oxide material) is formed over the conductive material and a fill material (e.g.