Abstract: A resist pattern formed so as to expose a wafer edge region is used to expose an edge surface region of an Si support substrate by dry etching. Next, a conductive layer constituted as wirings by subsequent patterning is formed by sputtering.

Abstract: A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).

Abstract: Mixed metal aluminum nitride and boride diffusion barriers and electrodes for integrated circuits, particularly for DRAM cell capacitors. Also provided are methods for CVD deposition of MxAlyNzBw alloy diffusion barriers, wherein M is Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, or W; x is greater than zero; y is greater than or equal to zero; the sum of z and w is greater than zero; and wherein when y is zero, z and w are both greater than zero.

Abstract: A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.

Abstract: A bumping process mainly comprises the following steps. Initially, a wafer having a plurality of bonding pads and a passivation layer, which exposes the bonding pads, is provided. Next, a first dielectric layer is disposed on the wafer so as to form a plurality of first openings and second openings. The first openings and the second openings expose the bonding pads and the passivation layer respectively. Afterward, a patterned first electrically conductive layer is formed on the first dielectric layer, the bonding pads and the passivation layer exposed out of the first dielectric layer through the second openings. Then, a second patterned conductive layer is formed directly on the first patterned conductive layer.

Abstract: A method of manufacturing a semiconductor device characterized by its high-speed operation and high reliability is provided in which a semiconductor layer crystallized by a CW laser is used for an active layer of a TFT. When a semiconductor layer is crystallized by a CW laser, one part is formed of large crystal grains whereas another part is formed of microcrystals due to the width-wise energy density distribution. The former exhibits excellent electric characteristics. The latter has poor electric characteristics because grain boundaries hinder movement of electric charges, and therefore causes inconveniences when used as an active layer of a transistor. Accordingly, circuits are arranged such that a semiconductor layer formed of large crystal grains is used for the active layer of every TFT.

Abstract: A metal electrode is formed on a substrate. The metal electrode includes a first layer, a second layer, and a third layer lying, from an outermost surface of the metal electrode toward the substrate, in this order. The first layer contains tin as a principal constituent and the second layer contains a metallic element which produces an eutectic reaction with tin, wherein the melting point of the first layer is higher than the melting point of the second layer. The third layer is an underlying metallic layer for the first and second layers.

Abstract: Disclosed are methods of manufacturing semiconductor devices, which may solve problems such as a short of upper wiring, etc., which are caused by a metal residue generated during chemical mechanical polishing of metallization of the semiconductor device, by depositing a predetermined insulating layer on the metal residue. The method may include forming a first insulating layer having an opening on a semiconductor substrate, depositing a metal layer on the first insulating layer to sufficiently fill the opening, planarizing the metal layer to expose the first insulating layer, forming a second insulating layer on the exposed first insulating layer and the metal layer, selectively etching and removing the second insulating layer to expose the metal layer, and forming a metallization layer on the metal layer.

Abstract: An etch resistant liner covering sidewalls of a transistor gate stack and along a portion of the substrate at a base of the transistor gate stack. The liner prevents silicide formation on the sidewalls of the gate stack, which may produce electrical shorting, and determines the location of silicide formation within source and drain regions within the substrate at the base of the transistor gate stack. The liner also covers a resistor gate stack preventing silicide formation within or adjacent to the resistor gate stack.

Abstract: A method of processing a semiconductor wafer includes utilizing a heated gas to heat at least one part of a semiconductor wafer by convection whereupon at least one contaminant is desorbed therefrom. A stream of cooling gas is caused to pass over the one part of the semiconductor wafer in the absence of heated gas to cool the one part of the semiconductor wafer. A metrology tool is then caused to measure at least one part of the semiconductor wafer to determine at least one characteristic thereof.

Abstract: A high-density multi-chip module and method for construction thereof, wherein a plurality of integrated circuit dice with at least one row of generally central bond pads is bonded in a staggered flip-chip style to opposite sides of a metallized substrate. The bond pads of each die are positioned over a through-hole in the substrate, and the bond pads are wire-bonded from one side of the substrate to circuitry on the opposing side of the substrate. Application of a glob-top sealant into the through-holes seals the bond pads and bond wires. A ball grid array may be formed in the peripheral area surrounding the dice on one side of the substrate, or an edge connection may be incorporated for connection to an external circuit.

Abstract: The present invention provides a method of manufacturing a semiconductor device which includes a step of forming a laminated film for pattern formation on a substrate, in which the laminated film for pattern formation includes an innermost layer, an inner layer and a surface layer, an extinction coefficient k of the innermost layer is 0.3 or more, and an extinction coefficient k of the inner layer is 0.12 or more. It also provides a method of forming a pattern which includes a step of forming a laminated film for pattern formation on a substrate, in which the laminated film for pattern formation includes an innermost layer, an inner layer and a surface layer, an extinction coefficient k of the innermost layer is 0.3 or more, and an extinction coefficient k of the inner layer is 0.12 or more.

Abstract: A method for forming a junction region of a semiconductor device is disclosed. The steps of the method include providing a semiconductor substrate. A gate structure is formed on the semiconductor substrate. A dopant is implanted into the semiconductor substrate to form the junction region. An insulator layer is formed on the gate structure and the semiconductor substrate. A carbon-containing plasma treatment is performed to the insulator layer. A spacer is formed on a side-wall of the gate structure and the dopant is implanted into the semiconductor substrate to form a source/drain region next to the junction region. A heat treatment is performed to the semiconductor substrate.

Abstract: The invention relates to a film or a layer made of semi-conducting material with low defect density in the thin layer, and a SOI-disk with a thin silicon layer exhibiting low surface roughness, defect density and thickness variations. The invention also relates to a method for producing a film or a layer made of semi-conductive material. Said method comprises the following steps: a) producing structures from a semi-conductive material with periodically repeated recesses which have a given geometrical structure, b) thermally treating the surface structured material until a layer with periodically repeated hollow spaces is formed under a closed layer on the surface of the material, c) separating the closed layer on the surface along the layer of hollow spaces from the remainder of the semi-conductive material.

Abstract: A method and apparatus for plating facilitates the plating of a small contact feature of a wafer die while providing a relatively stable plating bath. The method utilizes a supplemental plating structure that is larger than a die contact that is to be plated. The supplemental plating structure may be located on the wafer, and is conductively connected to the die contact. Conductive connection between the die contact and the supplemental plating structure facilitates the plating of the die contact. The supplemental plating structure also can be used to probe test the die prior to singulation.

Abstract: A semiconductor device which is manufactured through a process of forming a second structure on a first structure, by using a photolithography technique, the semiconductor device includes a mark which is provided at a part of the first structure to be covered by the second structure and which is necessary for forming the second structure.

Abstract: Resin cloths, powders, specular bodies and other objects resistant to conventional plating can be plated with metals by a simple method. According to the metal plating method of the present invention, electroless plating is performed after the surface of a object to be plated is treated with a pretreatment agent obtained by reacting or mixing in advance a noble metal compound (catalyst) with a silane-coupling agent having functional groups capable of capturing metals. According to this method, metal plating can be securely applied to powders, resin cloths, semiconductor wafers, and other specular bodies. Moreover, the problem of the insufficient coverage of the seed layer on the inside walls of vias and trenches during the formation of fine wiring can be addressed by applying this method to semiconductor wafers. The silane-coupling agent may be a compound containing azole groups, preferably an imidazole.

Abstract: Methods of forming an electronic device including a substrate and a raised pattern on the substrate are provided. For example, a first insulating layer may be formed on the raised pattern and on the substrate. More particularly, forming the first insulating layer may include forming a first portion of the first insulating layer using a first processing condition and forming a second portion of the first insulating layer using a second processing condition. After forming the first insulating layer including the first and second portions, portions of the first insulating layer may be removed to expose portions of the raised pattern while maintaining portions of the first insulating layer on the substrate. After removing portions of the first insulating layer, a second insulating layer may be formed on the exposed portions of the raised pattern and on the maintained portions of the first insulating layer.

Abstract: A metallization insulating structure, having a substrate; a substantially fluorine free insulating layer formed on the substrate, having a height, hi; a fluorine containing insulating layer formed on the substantially fluorine free insulating layer, having a height hf.

Abstract: A MIM capacitor can be formed by forming an insulating layer on a source/drain region of a transistor. A first pattern is formed on the insulating layer. A recess is formed in the insulating layer using the first pattern, wherein the recess exposes the source/drain region. A first electrode layer is formed in the recess on the source/drain region. A dielectric layer and a second electrode layer are formed on the first electrode layer in the recess. A second pattern is formed on the second electrode layer. The MIM capacitor is formed by removing a portion of the second electrode and the dielectric layer using the second pattern.