Abstract: A semiconductor structure includes a substrate, a via, a conductive pillar, and a core layer. The via is located in the substrate. The conductive pillar is located in the via, and the conductive pillar is provided with a groove extended inwards from an upper surface of the conductive pillar. The core layer is located in the groove, a Young modulus of the core layer is less than that of the conductive pillar.

Abstract: A semiconductor component includes a radiation exit surface; a semiconductor body having an active region that generates radiation; wherein a molded body molded onto the semiconductor body; contacts for external electrical contacting of the semiconductor component are accessible on an outer side of the molded body; a deflection structure arranged between the active region and the radiation exit surface; a planarization layer arranged on the deflection structure; and a polarizer arranged on a side of the planarization layer facing away from the semiconductor body; wherein the semiconductor body on a side facing away from the radiation exit surface includes a mirror structure having at least one dielectric layer and a metallic connection layer, and the dielectric layer is arranged at locations between the semiconductor body and the metallic connection layer.

Abstract: A method includes forming a first transistor stack over a substrate. The first transistor stack includes: a first transistor of a first conductivity type, and a second transistor of a second conductivity type different from the first conductivity type. The second transistor is above the first transistor. A plurality of first conductive lines is formed in a first metal layer above the first transistor stack. The plurality of first conductive lines includes, over the first transistor stack, a power conductive line configured to route power to the first transistor stack, one or more signal conductive lines configured to route one or more signals to the first transistor stack, and a shielding conductive line configured to shield the routed one or more signals. The one or more signal conductive lines are between the power conductive line and the shielding conductive line.

Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.

Abstract: A semiconductor device includes a first transistor, a second transistor, and a memory component. The first transistor includes a first silicon layer, a high-k gate dielectric layer above the first silicon layer, a first metal gate above the high-k gate dielectric layer, and first source/drain regions within the first silicon layer. The second transistor includes a second silicon layer, a first silicon oxide layer above the second silicon layer, a plurality of first doped silicon gates above the first silicon oxide layer, a plurality of second doped silicon gates above the first silicon oxide layer and alternately arranged with the plurality of first doped silicon gates, and second source/drain regions within the second silicon layer. The memory component is above the first and second transistors, and electrically coupled to the second source or drain region.

Abstract: A diode having a simple structure and a simple manufacturing method of the diode are provided. A diode including: a semiconductor layer having a first region and a second region having a resistance lower than a resistance of the first region; a first insulating layer having a first aperture portion and a second aperture portion and covering the semiconductor layer other than the first aperture and the second aperture, the first aperture portion exposing the semiconductor layer in the first region, the second aperture portion exposing the semiconductor layer in the second region; a first conductive layer connected to the semiconductor layer in the first aperture portion and overlapping with the semiconductor layer in the first region via the first insulating layer in a planar view; and a second conductive layer connected to the semiconductor layer in the second aperture.

Abstract: A wide band gap semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer, first, second, and third regions having particular conductivity types and defining sides of the trench, and a first electrode embedded inside an insulating film in the trench. The second region integrally includes a first portion arranged closer to a first surface of the semiconductor layer than to a bottom surface of the trench, and a second portion projecting from the first portion toward a second surface of the semiconductor layer to a depth below a bottom surface of the trench. The second portion of the second region defines a boundary surface with the third region, the boundary region being at an incline with respect to the first surface of the semiconductor layer.

Abstract: A semiconductor device including: a semiconductor substrate including an active region; a plurality of conductive structures formed over the semiconductor substrate; an isolation layer filling a space between the conductive structures and having an opening that exposes the active region between the conductive structures; a pad formed in a bottom portion of the opening and in contact with the active region; a plug liner formed conformally over a sidewall of the opening and exposing the pad; and a contact plug formed over the pad inside the opening.

Abstract: A semiconductor device includes an active region, a LOCOS region formed within the active region and that extends vertically above a top surface of the active region, a gate region formed above the top surface of the active region, and a polysilicon resistor having a bottom surface that is offset vertically and physically isolated from a top surface of the LOCOS region. The active region includes a source region laterally disposed from the gate region, a drain region laterally disposed from the gate region, and a drift region laterally disposed between the gate region and the drain region. The polysilicon resistor is formed above the drift region. The active region further includes a first charge balance region formed in the active region below the drift region.

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a substrate, and a drain region disposed within the substrate and separated from the source region. A plurality of separate isolation structures are disposed within the substrate. The plurality of separate isolation structures have outermost sidewalls that face one another and that are separated from one another. A gate electrode is disposed within the substrate. The gate electrode includes a base region disposed between the source region and the plurality of separate isolation structures and a plurality of gate extensions extending outward from a sidewall of the base region to over the plurality of separate isolation structures.

Abstract: A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.

Abstract: A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.

Abstract: Semiconductor package includes substrate, first barrier layer, second barrier layer, routing via, first routing pattern, second routing pattern, semiconductor die. Substrate has through hole with tapered profile, wider at frontside surface than at backside surface of substrate. First barrier layer extends on backside surface. Second barrier layer extends along sidewalls of through hole and on frontside surface. Routing via fills through hole and is separated from sidewalls of through hole by at least second barrier layer. First routing pattern extends over first barrier layer on backside surface and over routing via. First routing pattern is electrically connected to end of routing via and has protrusion protruding towards end of routing via in correspondence of through hole. Second routing pattern extends over second barrier layer on frontside surface. Second routing pattern directly contacts another end of routing via. Semiconductor die is electrically connected to routing via by first routing pattern.

Abstract: In examples, a method of forming a semiconductor package comprises forming a conversion coating solution comprising a salt of a vanadate, a salt of a zirconate, or both with a complexing agent; cleaning a copper lead frame, wherein the cleaned copper lead frame comprises copper oxide on an outer surface thereof; immersing the cleaned copper lead frame in the conversion coating solution; rinsing the copper lead frame; and forming an assembly by coupling a semiconductor die to the copper lead frame, coupling the semiconductor die to a lead of the copper lead frame, applying a mold compound onto at least a portion of the outer surface of the copper lead frame, and curing the mold compound. An adhesion strength at an interface between the mold compound and the at least the portion of the outer surface of the copper lead frame is increased relative to a same assembly formed without immersing the copper lead frame in the conversion coating solution.

Abstract: An LED module includes a first protrusion and a second protrusion adjacent to the first protrusion arranged on an insulating surface, a first electrode arranged on the first protrusion, and a second electrode arranged on the second protrusion, and an LED chip arranged on upper sides of the first protrusion and the second protrusion. The LED chip is connected to the first electrode and the second electrode via conductive members, and the first protrusion and the second protrusion are insulative and have a height of 1 ?m to 50 ?m.

Abstract: A semiconductor device including an active pattern; a gate structure connected to the active pattern; a bit line structure connected to the active pattern; a buried contact connected to the active pattern; a contact pattern covering the buried contact; a landing pad connected to the contact pattern; and a capacitor structure connected to the landing pad, wherein the buried contact includes a first growth portion and a second growth portion spaced apart from each other, and the landing pad includes an interposition portion between the first growth portion and the second growth portion.

Abstract: The present invention provides a display device using a semiconductor light-emitting element and a manufacturing method therefor, the display device transferring semiconductor light-emitting elements on a temporary substrate, and then directly implementing, through a stack process, the structure of a wiring substrate on the temporary substrate on which the semiconductor light-emitting elements are arrayed, thereby enabling the semiconductor light-emitting elements and the wiring substrate to be electrically connected.

Abstract: A device includes a substrate, an isolation structure over the substrate, a gate structure over the isolation structure, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer and on a top surface of the isolation structure, wherein a bottom surface of the dielectric liner is above a top surface of the silicide layer and spaced away from the top surface of the silicide layer in a cross-sectional plane perpendicular to a lengthwise direction of the gate structure.

Abstract: A trench power semiconductor device includes a substrate, an epitaxial layer, a drain, a first active device, a second active device, and isolation trench structures. The epitaxial layer and the drain are disposed on two surfaces of the substrate, respectively. The first active device is disposed in a first portion of the epitaxial layer and has a first source and a first gate. The second active device is disposed in a second portion of the epitaxial layer and has a second source and a second gate. The isolation trench structures are disposed between the first portion and the second portion of the epitaxial layer to electrically isolate the first active device and the second active device. Each of the isolation trench structures includes a polysilicon structure with a floating potential and an insulating layer. The insulating layer is between the polysilicon structure and the epitaxial layer.