Patents Examined by Chuong A Luu
  • Patent number: 10297502
    Abstract: A semiconductor structure suitable for micro-transfer printing includes a semiconductor substrate and a patterned insulation layer disposed on or over the semiconductor substrate. The insulation layer pattern forms one or more etch vias in contact with the semiconductor substrate. Each etch via is exposed. A semiconductor device is disposed on the patterned insulation layer and is surrounded by an isolation material in one or more isolation vias that are adjacent to the etch via. The etch via can be at least partially filled with a semiconductor material that is etchable with a common etchant as the semiconductor substrate. Alternatively, the etch via is empty and the semiconductor substrate is patterned to form a gap that separates at least a part of the semiconductor device from the semiconductor substrate and forms a tether physically connecting the semiconductor device to an anchor portion of the semiconductor substrate or the patterned insulation layer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: May 21, 2019
    Assignees: X-Celeprint Limited, X-FAB Semiconductor Foundries AG
    Inventors: Christopher Andrew Bower, Ronald S. Cok, William Andrew Nevin, Gabriel Kittler
  • Patent number: 10297529
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: May 21, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10297560
    Abstract: A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Che Ho, Hung-Jui Kuo, Yi-Wen Wu, Tzung-Hui Lee
  • Patent number: 10290725
    Abstract: A bipolar junction transistor includes a semiconductor substrate, a fin structure, an epitaxial emitter, an epitaxial collector and a gate. The fin structure is disposed on the semiconductor substrate and has a base portion of a first conductivity type, a first recessed portion and a second recessed portion. The epitaxial emitter of a second conductivity type is disposed in the first recessed portion of the fin structure. The epitaxial collector of the second conductivity type is disposed in the second recessed portion of the fin structure. The gate is disposed on the base portion of the fin structure and isolated from the base portion of the fin structure.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Hao Chu, Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang
  • Patent number: 10290536
    Abstract: Various self-aligned interconnect structures are disclosed herein. An exemplary interconnect structure includes a first dielectric layer disposed over a substrate; a first conductive feature disposed in the first dielectric layer; an etch stop layer disposed over a top surface of the first dielectric layer and a top surface of the first conductive feature; a second dielectric layer disposed over the first dielectric layer; and a second conductive feature disposed in the second dielectric layer. The top surface of the first conductive feature is lower than the top surface of the first dielectric layer. The etch stop layer includes a portion that extends between the top surface of the first conductive feature and the top surface of the first dielectric layer, on which the second conductive feature may or may not be disposed. In some implementations, the second conductive feature may be a via feature.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Tien-I Bao
  • Patent number: 10283513
    Abstract: A memory opening is formed through an alternating stack of insulating layers and sacrificial material layers located over a substrate. Annular recesses are formed around the memory opening by laterally recessing the sacrificial material layers with respect to the insulating layers. Annular metal portions are formed over recessed sidewalls of the sacrificial material layers within each of the annular recesses by a selective deposition process. Annular backside blocking dielectrics are formed selectively on inner sidewalls of the annular metal portions employing a layer of a self-assembly material that covers surfaces of the insulating layers and inhibits deposition of a dielectric material thereupon. A memory stack structure is formed in the memory opening, and the sacrificial material layers are replaced with electrically conductive layers. The annular backside blocking dielectrics provide electrical isolation for the annular metal portions, which function as control gate electrodes.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: May 7, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fei Zhou, Raghuveer S. Makala, Rahul Sharangpani, Adarsh Rajashekhar
  • Patent number: 10276548
    Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
  • Patent number: 10276763
    Abstract: Light emitting devices (LEDs) are described herein. An LED includes a light emitting semiconductor structure, a wavelength converting material and an off state white material. The light emitting semiconductor structure includes a light-emitting active layer disposed between an n-layer and a p-layer. The wavelength converting material has a first surface adjacent the light emitting semiconductor structure and a second surface opposite the first surface. The off state white material is in direct contact with the second surface of the wavelength converting material and includes multiple core-shell particles disposed in an optically functional material. Each of the core-shell particles includes a core material encased in a polymer or inorganic shell. The core material includes a phase change material.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: April 30, 2019
    Assignee: Lumileds LLC
    Inventors: Daniel Estrada, Ken Shimizu, Daniel Roitman, Marcel Rene Bohmer, Edward Kang
  • Patent number: 10276371
    Abstract: Modified silicon-on-insulator (SOI) substrates having a trap rich layer, and methods for making such modifications. The modified regions eliminate or manage accumulated charge that would otherwise arise because of the interaction of the underlying trap rich layer and active layer devices undergoing transient changes of state, thereby eliminating or mitigating the effects of such accumulated charge on non-RF integrated circuitry fabricated on such substrates. Embodiments retain the beneficial characteristics of SOI substrates with a trap rich layer for RF circuitry requiring high linearity, such as RF switches, while avoiding the problems of a trap rich layer for circuitry that is sensitive to accumulated charge effects caused by the presence of the trap rich layer, such as non-RF analog circuitry and amplifiers (including power amplifiers and low noise amplifiers).
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: April 30, 2019
    Assignee: pSemi Corporation
    Inventors: Robert Mark Englekirk, Keith Bargroff, Christopher C. Murphy, Tero Tapio Ranta, Simon Edward Willard
  • Patent number: 10276722
    Abstract: A thin film transistor includes an oxide semiconductor layer including a channel region, and a source region and a drain region having a resistivity lower than that of the channel region; a gate insulating layer disposed on the channel region of the oxide semiconductor layer; a gate electrode disposed on the gate insulating layer; and an aluminum oxide layer covering the lateral surface of the gate insulating layer, and the source region and the drain region, wherein the gate insulating layer has a multi-layer structure including a first insulating layer and a second insulating layer, and the first insulating layer contains silicon oxide as a main component, and is disposed on and in contact with the channel region.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: April 30, 2019
    Assignee: JOLED INC.
    Inventors: Toshiaki Yoshitani, Shinichi Ushikura
  • Patent number: 10269699
    Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
  • Patent number: 10269912
    Abstract: A device comprises a metal gate structure over a substrate, wherein the metal gate structure comprises a first metal sidewall, a metal bottom layer, a first corner portion between the first metal sidewall and the metal bottom layer, wherein the first corner portion comprises a first step and a first ramp, a second metal sidewall and a second corner portion between the second metal sidewall and the metal bottom layer, wherein the second corner portion comprises a second step and a second ramp.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Soon Lim, Da-Yuan Lee, Kuang-Yuan Hsu
  • Patent number: 10270061
    Abstract: An organic EL display device including a TFT substrate (substrate) and an organic EL element (electroluminescent element) that is provided on the TFT substrate includes a sealing layer that seals the organic EL element. The sealing layer is composed of a laminated structure that is constituted by an organic film and first and second inorganic films. Recessed/protruding portions are provided on surfaces of the organic film and the first and second inorganic films.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: April 23, 2019
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Sonoda, Takeshi Hirase, Tetsuya Okamoto, Tohru Senoo, Daichi Nishikawa, Mamoru Ishida
  • Patent number: 10263016
    Abstract: An active matrix substrate includes a first TFT (10), a second TFT (20) disposed per pixel, and a circuit including the first TFT. The first and second TFTs each include a gate electrode (102A, 102B), a gate insulating layer (103), an oxide semiconductor layer (104A, 104B), and source and drain electrodes in contact with an upper surface of the oxide semiconductor layer. The oxide semiconductor layer (104A, 104B) has a stacked structure including a first semiconductor layer (104e, 104c) in contact with the source and drain electrodes and a second semiconductor layer that is disposed on a substrate-side of the first semiconductor layer and that has a smaller energy gap than the first semiconductor layer. The oxide semiconductor layers (104A) and (104B) are different from each other in terms of the composition and/or the number of stacked layers. The first TFT has a larger threshold voltage than the second TFT.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: April 16, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hisao Ochi, Tohru Daitoh, Hajime Imai, Tetsuo Fujita, Hideki Kitagawa, Tetsuo Kikuchi, Masahiko Suzuki, Teruyuki Ueda
  • Patent number: 10263209
    Abstract: Disclosed is a fluorescent/phosphorescent mixed white organic light-emitting diode, which has high efficiency and good spectral stability.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: April 16, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Wei Yuan, Aiguo Tu
  • Patent number: 10263139
    Abstract: A fabrication method of a nitride semiconductor LED includes, an AlxInyGa1-x-yN material layer is deposited by CVD between an AlN thin film layer by PVD and a gallium nitride series layer by CVD, to reduce the stress effect between the AlN thin film layer and the nitride layer, improve the overall quality of the LED and efficiency. An AlN thin film layer is deposited on a patterned substrate having a larger depth by PVD, and a thin nitrogen epitaxial layer is deposited on the AIN thin film layer by CVD, which reduces the stress by reducing the thickness of the epitaxial layer and improves warpage of the wafer and electric uniformity of the single wafer; the light extraction efficiency is improved by using the large depth patterned substrate; further, the doping of high-concentration impurity in the active layer effectively reduces voltage characteristics without affecting leakage, thereby improving the overall yield.
    Type: Grant
    Filed: January 8, 2017
    Date of Patent: April 16, 2019
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Hsiang-lin Hsieh, Zhibo Xu, Cheng-hung Lee, Chan-chan Ling, Chang-cheng Chuo, Chia-hung Chang
  • Patent number: 10262986
    Abstract: A protection device as provided includes a doped well with a first-type impurity, formed in a substrate. A first semiconductor terminal with a second-type impurity is formed on the doped well. A second semiconductor terminal with a second-type impurity is formed on the doped well separating from the first semiconductor terminal. The first semiconductor terminal is connected to a voltage level and a second semiconductor terminal is connected to a ground voltage.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: April 16, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Sheng-Huei Dai, Tzung-Lin Li
  • Patent number: 10256162
    Abstract: Disclosed is a substrate processing system capable of performing an etching processing collectively on a plurality of substrates accommodated in a processing container. The system includes: a first acquisition unit which acquires, as information, an amount of a film forming material formed on one of the substrates; a second acquisition unit which acquires, as information, the number of the substrates; a first calculating unit which calculates a total amount of the film forming material formed on the substrates based on the amount of the film forming material and the number of the substrates; and a second calculating unit which calculates an etching condition required to etch and remove the entire film forming material based on the total amount of the film forming materials and a relationship between a predetermined amount of the film forming material and an etching condition.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: April 9, 2019
    Assignee: Tokyo Electron Limited
    Inventor: Masami Oikawa
  • Patent number: 10252454
    Abstract: A manufacturing method of a semiconductor device includes the steps of: preparing a lead frame; mounting a plurality of semiconductor chips on the lead frame; and sealing one portion of the lead frame with a sealing resin. The resin-sealing step includes the step of: disposing the lead frame, molds having main surfaces on which cavity parts are formed, the lead frame being disposed on the main surface of the heated molds; injecting a resin in the main surfaces of the heated molds so as to seal the one portion of the lead frame with the sealing resin; and taking out the lead frame from the heated molds. In the taking-out step, while the lead frame is taken out, the main surfaces of the molds are inspected by using a sensor, and the sensor is cooled and formed integrally with an arm used for taking out the lead frame.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: April 9, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Itaru Matsuo
  • Patent number: 10256267
    Abstract: A solid-state imaging device includes a plurality of photoelectric conversion portions each provided to correspond to each of a plurality of pixels in a semiconductor substrate and receiving incident light through a light sensing surface, and a pixel separation portion that is embedded into a trench provided on a side portion of the photoelectric conversion portion and electrically separates the plurality of pixels in a side of an incident surface of the semiconductor substrate into which the incident light enters. The pixel separation portion is formed by an insulation material which absorbs the incident light entering the light sensing surface.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 9, 2019
    Assignee: Sony Corporation
    Inventor: Yuki Miyanami