Patents Examined by Chuong A Luu
  • Patent number: 11121051
    Abstract: Semiconductor packages and methods of forming the same are disclosed. a semiconductor package includes a die and an underfill. The die is disposed over a surface and includes a first sidewall. The underfill encapsulates the die. The underfill includes a first underfill fillet on the first sidewall, and in a cross-sectional view, a second sidewall of the first underfill fillet has a turning point.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu, Chih-Chien Pan
  • Patent number: 11120739
    Abstract: A display device including a substrate and a plurality of pixels in a display region of the substrate. Each of the pixels includes first and second sub-pixels, and each of the first and second sub-pixels has a light emitting region for emitting light. The first sub-pixel includes a first light emitting element in the light emitting region and configured to emit visible light. The second sub-pixel includes a second light emitting element in the light emitting region and configured to emit infrared light and a light receiving element configured to receive the infrared light emitted from the second light emitting element to detect a user's touch. The second light emitting element and the light receiving element in the second sub-pixel are electrically insulated from and optically coupled to each other to form a photo-coupler.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: September 14, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun Min Cho, Dae Hyun Kim, Sung Chul Kim, Hye Yong Chu, Keun Kyu Song
  • Patent number: 11121088
    Abstract: A method of manufacturing a semiconductor package structure is provided. The method includes providing a first carrier, forming a patterned buffer layer over the first carrier, forming a first redistribution structure that includes forming a first dielectric layer on the patterned buffer layer, after an electrical testing by applying an electric signal towards the first redistribution structure, removing the first carrier, removing portions of the first dielectric layer, resulting in a patterned first dielectric layer, the patterned first dielectric layer exposing portions of the first circuit layer, removing the exposed portions of the first circuit layer, using the patterned first dielectric layer as a mask, resulting in a patterned first circuit layer, and forming an electric conductor in a recess defined by the patterned first dielectric layer and the patterned first circuit layer.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: September 14, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Ting-Yang Chou
  • Patent number: 11121286
    Abstract: A semiconductor device according to an embodiment includes a substrate, first and second light emitting structures disposed on the substrate, a first reflective electrode disposed on the first light emitting structure, a second reflective electrode disposed on the second light emitting structure, a connection electrode, a first electrode pad, and a second electrode pad. According to the embodiment, the first light emitting structure includes a first semiconductor layer of a first conductivity type, a first active layer disposed on the first semiconductor layer, a second semiconductor layer of a second conductivity type and disposed on the first active layer, and a first through hole provided through the second semiconductor layer and the first active layer to expose the first semiconductor layer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 14, 2021
    Assignee: SUZHOU LEKTN SEMICONDUCTOR CO., LTD.
    Inventor: Jae Won Seo
  • Patent number: 11114415
    Abstract: A semiconductor device includes a first die; a second die attached over the first die; a metal enclosure directly contacting and extending between the first die and the second die, wherein the first metal enclosure is continuous and encircles a set of one or more internal interconnects, wherein the first metal enclosure is configured to electrically connect to a first voltage level; and a second metal enclosure directly contacting and extending between the first die and the second die, wherein the second metal enclosure is continuous and encircles the first metal enclosure and is configured to electrically connect to a second voltage level; wherein the first metal enclosure and the second metal enclosure are configured to provide an enclosure capacitance encircling the set of one or more internal interconnects for shielding signals on the set of one or more internal interconnects.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: September 7, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Wei Zhou, Bret K. Street
  • Patent number: 11114573
    Abstract: An optoelectronic module assembly includes an optoelectronic module. The module includes: an active optoelectronic component in or on a mounting substrate, an optical sub-assembly, and a spacer disposed between the mounting substrate and the optical sub-assembly so as to establish a particular distance between the active optoelectronic component and the optical sub-assembly. The optoelectronic module assembly also includes a recessed substrate including first and second surfaces, wherein the second surface is in a plane closer to the optical sub-assembly than is the first surface. The optoelectronic module is mounted on the first surface. The second surface is for mounting other components.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: September 7, 2021
    Assignee: ams Sensors Singapore Pte. Ltd.
    Inventors: Martin Lukas Balimann, Matthias Gloor, Philippe Bouchilloux, Jukka Alasirnio, Hartmut Rudmann, Nicola Spring
  • Patent number: 11107814
    Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: August 31, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Junli Wang, Michael P. Belyansky
  • Patent number: 11107684
    Abstract: Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K, and Wherein the n-type donor atoms are introduced to the lattice through ion tracks.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: August 31, 2021
    Assignee: AKHAN Semiconductor, Inc.
    Inventor: Adam Khan
  • Patent number: 11101298
    Abstract: A thin film transistor array substrate includes: a first conductive layer including first lines for transmitting data signals to the thin film transistors; a second conductive layer disposed on the first conductive layer and including second lines for supplying a driving voltage to the thin film transistors; a first insulating layer disposed between a semiconductor layer and the first conductive layer and including a first material layer; a second insulating layer disposed between the first conductive layer and the second conductive layer and including a second material layer having a dielectric constant greater than that of the first material layer; and a contact plug penetrating the second insulating layer and the first insulating layer, and connecting the second conductive layer to the semiconductor layer. A taper angle of the contact plug in the second material layer is greater than that of the contact plug in the first material layer.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: August 24, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jinwoo Lee, Waljun Kim, Kiwan Ahn, Yongjae Jang, Jaehyuk Jang, Yugwang Jeong
  • Patent number: 11101177
    Abstract: A method for forming a semiconductor structure includes: providing a substrate; forming a stacked structure on the substrate; forming a barrier layer on a sidewall of the stacked structure; forming a first dielectric layer covering the barrier layer and the stacked structure; removing a portion of the first dielectric layer to expose an upper portion of the stacked structure; forming a metal layer covering the stacked structure and the first dielectric layer; performing an annealing process to react the metal layer with the stacked structure to form a metal silicide layer at the upper portion of the stacked structure; removing an unreacted portion of the metal layer; removing a portion of the barrier layer to form a recess above the barrier layer; and forming a second dielectric layer covering the metal silicide layer and the first dielectric layer to form air gaps on both sides of the stacked structure.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: August 24, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Che-Jui Hsu, Chun-Sheng Lu, Ying-Fu Tung, Mao-Chang Yen, Wan-Yu Peng
  • Patent number: 11088070
    Abstract: A method of forming a multi-level interconnect structure in a semiconductor device is disclosed. In one aspect, the device includes a first interconnection level including a first dielectric layer and a first conductive structure; a second interconnection level including a second dielectric layer and a second conductive structure; and a third interconnection level including a third dielectric layer and a third conductive structure. The method includes forming a trench in the third dielectric layer; providing a first sacrificial material in the trench; and thereafter forming a via extending through the third interconnection level to the second conductive structure; providing a second sacrificial material in the via; forming a multi-level via extending through the third interconnection level to the first conductive structure; removing the first and second sacrificial materials; and depositing a conductive material at least partially filling: the trench; the via; and the multi-level via.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: August 10, 2021
    Assignee: IMEC vzw
    Inventors: Basoene Briggs, Vladimir Machkaoutsan, Zsolt Tokei
  • Patent number: 11088104
    Abstract: A process for forming an electric heater comprising the steps: (a) providing a heater element and a power supply, (b) applying a layer of a copper paste onto the heater element and/or the power supply and drying the applied layer of copper paste, (c1) applying a solder agent onto the dried copper paste and appropriately arranging the heater element and the power supply such that the heater element and the power supply contact each other by means of the dried copper paste and the solder agent or (c2) appropriately arranging the heater element and the power supply such that the heater element and the power supply contact each other by means of the dried copper paste, and applying a solder agent next to the dried copper paste or (c3) if in step (b) the copper paste has been applied only onto the heater element and then dried, applying a solder agent onto the power supply and appropriately arranging the heater element and the power supply such that the heater element and the power supply contact each other by me
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: August 10, 2021
    Assignee: HERAEUS PRECIOUS METALS NORTH AMERICA CONSHOHOCKEN LLC
    Inventors: Ryan Persons, Sebastian Fritzsche, Steffan Käss, Tanja Dickel
  • Patent number: 11081562
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a gate stack positioned on the substrate, a plurality of programmable contacts positioned on the gate stack, a pair of heavily-doped regions positioned adjacent to two sides of the gate stack and in the substrate, and a plurality of first contacts positioned on the pair of heavily-doped regions. A width of the plurality of programmable contacts is less than a width of the plurality of first contacts.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: August 3, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chin-Ling Huang
  • Patent number: 11075220
    Abstract: A semiconductor device includes a first stacked body comprising first conductive layers and first insulating layers interposed therebetween, a first columnar portion comprising a first semiconductor layer extending in the first stacked body in the first direction and a first memory layer between the first semiconductor layer and the first conductive layers, a second stacked body comprising second conductive layers and second insulating layers interposed therebetween, and a second columnar portion comprising a second semiconductor layer extending in the second stacked body in the first direction and a second memory layer between the second semiconductor layer and the second conductive layers. The first columnar portion has a first diameter, and the second columnar portion has a second diameter, and each of the plurality of first conductive layers has a first film thickness, and each of the plurality of second conductive layers has a second film thickness.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: July 27, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Ken Komiya
  • Patent number: 11075162
    Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
  • Patent number: 11069652
    Abstract: A method of manufacturing a semiconductor structure is provided. The method includes providing a first substrate including a plurality of conductive bumps disposed over the first substrate; providing a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the plurality of conductive bumps is exposed through the patterned adhesive; bonding the first substrate with the second substrate; and singulating a chip from the first substrate.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Alexander Kalnitsky, Yi-Yang Lei, Hsi-Ching Wang, Cheng-Yu Kuo, Tsung Lung Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu, Chin-Yu Ku, De-Dui Liao, Kuo-Chio Liu, Kai-Di Wu, Kuo-Pin Chang, Sheng-Pin Yang, Isaac Huang
  • Patent number: 11060026
    Abstract: An electroluminescent device includes a first electrode and a second electrode facing each other, and an emissive layer disposed between the first electrode and the second electrode and including the quantum dots. The quantum dots include a semiconductor nanocrystal core including indium (In) and phosphorous (P), a first semiconductor nanocrystal shell disposed on the semiconductor nanocrystal core, the first semiconductor nanocrystal shell including zinc and selenium, and a second semiconductor nanocrystal shell disposed on the first semiconductor nanocrystal shell, the second semiconductor nanocrystal shell including zinc and sulfur, wherein the quantum dots do not include cadmium. The electroluminescent device has an external quantum efficiency of greater than or equal to about 9% and a maximum brightness of greater than or equal to about 10,000 candelas per square meter (cd/m2).
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: July 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yuho Won, Ha Il Kwon, Eun Joo Jang, Jaejun Chang, Dae Young Chung
  • Patent number: 11062954
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: July 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Patent number: 11062938
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: July 13, 2021
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Patent number: 11049859
    Abstract: The present disclosure relates to a bulk complementary-metal-oxide-semiconductor (CMOS) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the thinned device die. Herein, a silicon material with a resistivity between 5 Ohm-cm and 30000 Ohm-cm does not exist between the second mold compound and the thinned device die.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 29, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll, Dirk Robert Walter Leipold, George Maxim, Baker Scott