Patents Examined by Chuong A Luu
  • Patent number: 10727305
    Abstract: A semiconductor device includes a nitride semiconductor stacked structure that includes a channel layer containing GaN and a barrier layer containing In and further includes a cap layer that contains GaN on the outermost surface but does not contain Al. The cap layer has a Ga/N ratio that varies along a thicknesswise direction.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 28, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Kozo Makiyama
  • Patent number: 10720469
    Abstract: The present invention is directed to a magnetic structure including a first seed layer, a second seed layer formed on top of the first seed layer, and a third seed layer made of chromium or iridium formed on top of the second seed layer. One of the first and second seed layers comprises cobalt, iron, and boron. The other one of the first and second seed layers is made of iridium, rhodium, cobalt, platinum, palladium, nickel, ruthenium, or rhenium. The magnetic structure further includes a magnetic fixed layer structure formed on top of the third seed layer and having an invariable magnetization direction substantially perpendicular to a layer plane thereof. The magnetic fixed layer structure includes layers of a magnetic material interleaved with layers of a transition metal. The transition metal may be nickel, platinum, palladium, or iridium.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: July 21, 2020
    Assignee: Avalanche Technology, Inc.
    Inventors: Zihui Wang, Yiming Huai
  • Patent number: 10714387
    Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first direction parallel to a top surface of the substrate; a gate structure extending on the fin-type active region and extending in a second direction parallel to the top surface of the substrate and different from the first direction; and source/drain regions in a recess region extending from one side of the gate structure into the fin-type active region, the source/drain regions including an upper semiconductor layer on an inner wall of the recess region, having a first impurity concentration, and including a gap; and a gap-fill semiconductor layer, which fills the gap and has a second impurity concentration that is greater than the first impurity concentration.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-yeong Joe, Seok-hoon Kim, Jeong-ho Yoo, Seung-hun Lee, Geun-hee Jeong
  • Patent number: 10707259
    Abstract: There is provided a semiconductor device including: a plurality of bumps on a first semiconductor substrate; and a lens material in a region other than the plurality of bumps on the first semiconductor substrate, wherein a distance between a side of a bump closest to the lens material and a side of the lens material closest to the bump is greater than twice a diameter of the bump closest to the lens material, and wherein the distance between the side of the bump closest to the lens material and the side of the lens material closest to the bump is greater a minimum pitch of the bumps.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: July 7, 2020
    Assignee: Sony Corporation
    Inventors: Jun Ogi, Junichiro Fujimagari, Susumu Inoue, Atsushi Fujiwara
  • Patent number: 10700168
    Abstract: A wide band gap semiconductor device includes a first doping region of a first conductivity type and a second doping region of a second conductivity type. A drift portion of the second doping region has a first average net doping concentration lower than 1e17 cm?3. A highly doped portion of the second doping region has a second average net doping concentration higher than 5e18 cm?3. A compensation portion of the second doping region located between the drift and highly doped portions extends from a first area with a net doping concentration higher than 1e16 cm?3 and lower than 1e17 cm?3 to a second area with a net doping concentration higher than 5e18 cm?3. A maximum gradient of the net doping concentration within at least a part of the compensation portion extending from the second area towards the first area for at least 100 nm is lower than 5e22 cm?4.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies AG
    Inventors: Josef Lutz, Roland Rupp, Hans-Joachim Schulze
  • Patent number: 10692786
    Abstract: A semiconductor structure includes a substrate, a first insulating layer, a second insulating layer, a first seal ring structure, a second seal ring structure, and a passivation layer. The substrate has a chip region and a seal ring region. The first insulating layer is on the substrate. The second insulating layer is on the first insulating layer. The first seal ring structure is in the seal ring region and embedded in the first insulating layer and the second insulating layer, wherein the first seal ring structure includes a stack of metal layers. The second seal ring structure is in the seal ring region and embedded in the first insulating layer, wherein the second seal ring structure includes a polysilicon ring structure. The passivation layer is on the second insulating layer and the first seal ring structure.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 23, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Ting-You Lin, Chi-Li Tu, Shin-Cheng Lin, Yu-Hao Ho, Cheng-Tsung Wu
  • Patent number: 10680056
    Abstract: A method of fabricating an integrated circuit (IC) includes providing a substrate having a semiconductor surface layer comprising an unpatterned resistive layer. Measurements are obtained of a characteristic of the unpatterned resistive layer at each of a plurality of locations over the substrate. The unpatterned resistive layer is modified, such as by targeted removal of layer material, in response to the measurements such that the measured characteristic is more uniform across the substrate. A resistor on the IC is defined from the unpatterned resistive layer after the modifying.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: June 9, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bhaskar Srinivasan, Brian Goodlin, Dhishan Kande
  • Patent number: 10680022
    Abstract: A solid state imaging device that includes a phase difference detection pixel which is a pixel for phase difference detection; a first imaging pixel which is a pixel for imaging and is adjacent to the phase difference detection pixel; and a second imaging pixel which is a pixel for imaging other than the first imaging pixel. An area of a color filter of the first imaging pixel is smaller than an area of a color filter of the second imaging pixel.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: June 9, 2020
    Assignee: Sony Corporation
    Inventors: Hiroshi Tayanaka, Yuuji Inoue, Masashi Nakata
  • Patent number: 10679970
    Abstract: A semiconductor device package is provided. The package can include a stack of semiconductor dies over a substrate, the substrate including a plurality of electrical contacts, and an annular interposer disposed over the substrate and surrounding the stack of semiconductor dies. The annular interposer can include a plurality of circuit elements each electrically coupled to at least a corresponding one of the plurality of electrical contacts. The package can further include a lid disposed over the annular interposer and the stack of semiconductor dies.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: June 9, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Thomas H. Kinsley
  • Patent number: 10658532
    Abstract: A method for fabricating thin-film optoelectronic devices (100), the method comprising: providing a alkali-nondiffusing substrate (110), forming a back-contact layer (120); forming at least one absorber layer (130) made of an ABC chalcogenide material, adding least one and advantageously at least two different alkali metals, and forming at least one front-contact layer (150) wherein one of said alkali metals comprise Rb and/or Cs and where, following forming said front-contact layer, in the interval of layers (470) from back-contact layer (120), exclusive, to front-contact layer (150), inclusive, the comprised amounts resulting from adding alkali metals are, for Rb and/or Cs, in the range of 500 to 10000 ppm and, for the other alkali metals, typically Na or K, in the range of 5 to 2000 ppm and at most 1/2 and at least 1/2000 of the comprised amount of Rb and/or Cs.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: May 19, 2020
    Assignee: FLISOM AG
    Inventors: Patrick Reinhard, Adrian Chirila
  • Patent number: 10651277
    Abstract: In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: May 12, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yuya Abiko, Natsuo Yamaguchi, Satoshi Eguchi
  • Patent number: 10651283
    Abstract: A method includes forming a trench over a substrate, wherein the trench is surrounded by gate spacers and an inter-layer dielectric layer, depositing a dielectric layer on a bottom and along sidewalls of the trench, depositing a metal layer over the dielectric layer, depositing a protection layer over the metal layer, wherein the protection layer has an uneven thickness, applying an etch-back process to the protection layer and the metal layer, wherein as a result of applying the etch-back process, a portion of the metal layer has been removed and at least a portion of the protection layer remains at the bottom of the trench and removing the protection layer from the trench.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Soon Lim, Da-Yuan Lee, Kuang-Yuan Hsu
  • Patent number: 10651042
    Abstract: A method of forming a contact to a semiconductor device that includes forming a vertically orientated channel region on semiconductor material layer of a substrate; and forming a first source/drain region in the semiconductor material layer. The method may continue with forming a metal semiconductor alloy contact on the first source/drain region extending along a horizontally orientated upper surface of the first source/drain region that is substantially perpendicular to the vertically orientated channel region, wherein the metal semiconductor alloy contact extends substantially to an interface with the vertically orientated channel region. Thereafter, a gate structure is formed on the vertically orientated channel region, and a second source/drain region is formed on the vertically orientated channel region.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: May 12, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10651287
    Abstract: A semiconductor structure includes a substrate, a semiconductor fin connected to the substrate, an epitaxial layer disposed over the semiconductor fin, and a silicide feature over and in contact with the epitaxial layer. The epitaxial layer including silicon germanium (SiGe) and further includes gallium (Ga) in an upper portion of the epitaxial layer that is in contact with the silicide feature.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chun Hsiung Tsai, Shih-Chieh Chang, Kuo-Feng Yu, Cheng-Yi Peng
  • Patent number: 10636755
    Abstract: An electronic product includes a substrate and a bonding pad structure. The bonding pad structure is disposed on the substrate, and the bonding pad structure includes a first metal layer, a first insulating layer, at least one first connecting hole and a transparent conductive layer. The first metal layer and the first insulating layer are disposed on the substrate. The first connecting hole is situated in the first insulating layer, and the first connecting hole exposes a portion of the first metal layer. The transparent conductive layer is disposed on the first insulating layer, and the transparent conductive layer has a first edge and a second edge opposite to the first edge, wherein the transparent conductive layer is electrically connected to the first metal layer through the first connecting hole. A spacing between the first edge and the first connecting hole is greater than or equal to 100 ?m.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: April 28, 2020
    Assignee: HANNSTAR DISPLAY CORPORATION
    Inventors: Hsuan-Chen Liu, Yu-Tuan Hsu
  • Patent number: 10629549
    Abstract: Provided are a device and method for generating an identification key using process variation during a bipolar junction transistor (BJT) process. A BJT may be produced by designing such that the effective base width of the BJT is at least a first threshold value but not more than a second threshold value, or, such that the total of the width of a second depletion region formed by connection with a collector region and the width of a first depletion region formed by connection with an emitter region, within a base region, differs from the width of the base region by a value that is at least the first threshold value but not more than the second threshold value. Whether or not there is a short circuit between the emitter region and the collector region is stochastically generated by means of process variation, and if ordinary turn-on voltage is not applied to the base in the produced BJT, whether or not there is a short circuit is identified by means of a reader and an identifier is provided.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: April 21, 2020
    Assignee: ICTK Holdings Co., Ltd.
    Inventors: Byong Deok Choi, Dong Kyue Kim
  • Patent number: 10629479
    Abstract: Various self-aligned interconnect structures are disclosed herein. An exemplary interconnect structure includes a first dielectric layer disposed over a substrate; a first conductive feature disposed in the first dielectric layer; an etch stop layer disposed over a top surface of the first dielectric layer and a top surface of the first conductive feature; a second dielectric layer disposed over the first dielectric layer; and a second conductive feature disposed in the second dielectric layer. The top surface of the first conductive feature is lower than the top surface of the first dielectric layer. The etch stop layer includes a portion that extends between the top surface of the first conductive feature and the top surface of the first dielectric layer, on which the second conductive feature may or may not be disposed. In some implementations, the second conductive feature may be a via feature.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: April 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Tien-I Bao
  • Patent number: 10629611
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 21, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Kiyohiko Sakakibara, Mitsuteru Mushiga, Hisakazu Otoi, Kenji Sugiura
  • Patent number: 10629528
    Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
  • Patent number: 10629520
    Abstract: A semiconductor device provided according to an aspect of the present disclosure includes a semiconductor element, a bonding target, a first wire, a wire strip and a second wire. The bonding target is electrically connected to the semiconductor element. The first wire is made of a first metal. The first wire includes a first bonding portion bonded to the bonding target and a first line portion extending from the first bonding portion. The wire strip is made of the first metal. The wire strip is bonded to the bonding target. The second wire is made of a second metal different from the first metal. The second wire includes a second bonding portion bonded to the bonding target via the wire strip and a second line portion extending from the second bonding portion.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: April 21, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Motoharu Haga