Patents Examined by Chuong A Luu
  • Patent number: 11569354
    Abstract: A method of manufacturing a recessed access device includes the following operations. A first trench is formed in a substrate. A first gate oxide layer is formed on an inner surface of the first trench. A sacrificial layer is formed in a bottom of the first trench, in which a portion of the first gate oxide layer above the sacrificial layer is exposed from the first trench. The portion of the first gate oxide layer is removed to expose a sidewall of the first trench. The sidewall of the first trench is oxidized to form a second gate oxide layer within the substrate, in which the second gate oxide layer is in contact with the first gate oxide layer. The sacrificial layer is removed to form a second trench.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: January 31, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kung-Ming Fan
  • Patent number: 11557548
    Abstract: A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: January 17, 2023
    Assignee: STMicroelectronics, Inc.
    Inventors: Aaron Cadag, Lester Joseph Belalo, Ela Mia Cadag
  • Patent number: 11557672
    Abstract: A wide band gap semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer, first, second, and third regions having particular conductivity types and defining sides of the trench, and a first electrode embedded inside an insulating film in the trench. The second region integrally includes a first portion arranged closer to a first surface of the semiconductor layer than to a bottom surface of the trench, and a second portion projecting from the first portion toward a second surface of the semiconductor layer to a depth below a bottom surface of the trench. The second portion of the second region defines a boundary surface with the third region, the boundary region being at an incline with respect to the first surface of the semiconductor layer.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: January 17, 2023
    Assignee: ROHM CO., LTD.
    Inventor: Kengo Omori
  • Patent number: 11551972
    Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first direction parallel to a top surface of the substrate; a gate structure extending on the fin-type active region and extending in a second direction parallel to the top surface of the substrate and different from the first direction; and source/drain regions in a recess region extending from one side of the gate structure into the fin-type active region, the source/drain regions including an upper semiconductor layer on an inner wall of the recess region, having a first impurity concentration, and including a gap; and a gap-fill semiconductor layer, which fills the gap and has a second impurity concentration that is greater than the first impurity concentration.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: January 10, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-yeong Joe, Seok-hoon Kim, Jeong-ho Yoo, Seung-hun Lee, Geun-hee Jeong
  • Patent number: 11545540
    Abstract: The present application provides an array substrate. The array substrate includes a base substrate; a plurality of light emitting elements on the base substrate; a plurality of driving thin film transistors for driving light emission of the plurality of light emitting elements, each of the plurality of driving thin film transistors including a first active layer; one or more power supply lines configured to supply a driving current respectively to the plurality of light emitting elements; and a light shielding layer configured to shield light from irradiating on the first active layer, the light shielding layer being electrically connected to at least one of the one or more power supply lines.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: January 3, 2023
    Assignee: Beijing BOE Technology Development Co., Ltd.
    Inventors: Pan Xu, Xiaoyun Liu
  • Patent number: 11545518
    Abstract: A method for fabricating an image sensor is described which includes forming an insulating layer on a semiconductor substrate and forming a recess in the semiconductor substrate and the insulating layer. An epitaxial structure is grown in the recess. A first polish treatment is then performed to the insulating layer and the epitaxial structure. The insulating layer is detected to obtain a signal intensity, and the signal intensity increases as a thickness of the insulating layer decreases. The first polish treatment stops when the signal intensity reaches a target value.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chiao-Chi Wang, Chung-Chuan Tseng, Chia-Ping Lai
  • Patent number: 11538922
    Abstract: A manufacturing method of an HEMT includes: forming a heterostructure; forming a first gate layer of intrinsic semiconductor material on the heterostructure; forming a second gate layer, containing dopant impurities of a P type, on the first gate layer; removing first portions of the second gate layer so that second portions, not removed, of the second gate layer form a doped gate region; and carrying out a thermal annealing of the doped gate region so as to cause a diffusion of said dopant impurities of the P type in the first gate layer and in the heterostructure, with a concentration, in the heterostructure, that decreases as the lateral distance from the doped gate region increases.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: December 27, 2022
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Ferdinando Iucolano
  • Patent number: 11532506
    Abstract: The present disclosure provides an integrated circuit structure with dielectric isolation structure for reducing capacitive coupling and crosstalk between conductive features and a method for preparing the same. The integrated circuit structure includes a plurality of conductive structures disposed over a substrate; a plurality of dielectric structures disposed over the conductive structures; an inter-layer dielectric (ILD) layer disposed over sidewalls of the dielectric structures and sidewalls of the conductive structures, wherein the ILD layer, the dielectric structure and the conductive structure form an air spacer therebetween; and a dielectric isolation structure including a liner layer enclosing an air gap in the ILD layer.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: December 20, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hung-Chi Tsai
  • Patent number: 11532697
    Abstract: A semiconductor structure includes a substrate, a first electrode over the substrate, a second electrode over the first electrode, and a first insulating layer between the first electrode and the second electrode. The first insulating layer has a first portion and a second portion coupled to the first portion, the second portion of the first insulating layer is in contact with the second electrode, the first portion is separated from the second electrode by the second portion. A thickness of the second portion is greater than a thickness of the first portion.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi Jen Tsai, Yuan-Tai Tseng, Chern-Yow Hsu
  • Patent number: 11515275
    Abstract: A semiconductor package includes a conductive pad, a semiconductor die with an aluminum bond pad over a dielectric layer of the semiconductor die, a gold bump on the aluminum bond pad, a first intermetallic layer of gold and aluminum between the aluminum bond pad and the gold bump, a copper ball bond on the gold bump, a second intermetallic layer of copper and gold between the copper ball bond and the gold bump, a copper wire extending from the copper ball bond to the conductive pad, a stitch bond between the copper wire and the conductive pad.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: November 29, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Lin Zhang, Huo Yun Duan, Xi Lin Li, Chen Xiong, Xiao Lin Kang
  • Patent number: 11515416
    Abstract: A transistor includes a trench formed in a semiconductor substrate. A conductive spacer is formed in the trench and offset from a first sidewall of the trench. A dielectric material is formed in the trench and surrounds the conductive spacer. A drift region is formed in the semiconductor substrate adjacent to the first sidewall and a first portion of a second sidewall of the trench. A drain region is formed in the drift region adjacent to a second portion of the second sidewall. A first gate region overlaps a portion of the drift region and is formed separate from the conductive spacer.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: November 29, 2022
    Assignee: NXP USA, INC.
    Inventor: Saumitra Raj Mehrotra
  • Patent number: 11515351
    Abstract: There is provided a semiconductor device in which the inter-wiring capacitance of wiring lines provided in any layout is further reduced. A semiconductor device (1) including: a first inter-wiring insulating layer (120) that is provided on a substrate (100) and includes a recess on a side opposite to the substrate; a first wiring layer (130) that is provided inside the recess in the first inter-wiring insulating layer; a sealing film (140) that is provided along an uneven shape of the first wiring layer and the first inter-wiring insulating layer; a second inter-wiring insulating layer (220) that is provided on the first inter-wiring insulating layer to cover the recess; and a gap (150) that is provided between the second inter-wiring insulating layer and the first wiring layer and the first inter-wiring insulating layer. The second inter-wiring insulating layer has a planarized surface that is opposed to the recess.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: November 29, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Masaki Haneda
  • Patent number: 11515389
    Abstract: A semiconductor device including: a semiconductor substrate including an active region; a plurality of conductive structures formed over the semiconductor substrate; an isolation layer filling a space between the conductive structures and having an opening that exposes the active region between the conductive structures; a pad formed in a bottom portion of the opening and in contact with the active region; a plug liner formed conformally over a sidewall of the opening and exposing the pad; and a contact plug formed over the pad inside the opening.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: November 29, 2022
    Assignee: SK hynix Inc.
    Inventor: Hae Jung Park
  • Patent number: 11502009
    Abstract: Various embodiments of a die carrier package and a method of forming such package are disclosed. The package includes one or more dies disposed within a cavity of a carrier substrate, where a first die contact of one or more of the dies is electrically connected to a first die pad disposed on a recessed surface of the cavity, and a second die contact of one or more of the dies is electrically connected to a second die pad also disposed on the recessed surface. The first and second die pads are electrically connected to first and second package contacts respectively. The first and second package contacts are disposed on a first major surface of the carrier substrate adjacent the cavity.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: November 15, 2022
    Assignee: Medtronic, Inc.
    Inventors: Mark R. Boone, Mark E. Henschel
  • Patent number: 11502194
    Abstract: An MOSFET manufacturing method, comprising: etching an oxide layer and a silicon nitride layer on a first conductivity type well region, and forming an opening exposing the first conductivity type well region; etching the first conductivity type well region to form a first trench; depositing a medium oxide layer and performing back etching; etching the first conductivity type well region to form a second trench that is connected to the first trench, and forming a grid on an inner wall of the second trench, forming a second conductivity type well region in the first conductivity type well region at the bottom of the second trench, and forming a source in the second conductivity type well region; and removing the oxide layer and the silicon nitride layer, and forming a drain at the first conductivity type well region outside of the trench.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: November 15, 2022
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventor: Tse-huang Lo
  • Patent number: 11495531
    Abstract: A semiconductor device package and a method for manufacturing the semiconductor device package are provided. The semiconductor device package includes a carrier, an electronic component, a first encapsulant and a conductive via. The carrier has a first surface and a second surface opposite to the first surface. The semiconductor device is mounted at the second surface of the carrier. The first encapsulant encapsulates the first surface of the carrier and has a surface facing away from the first surface of the carrier. The conductive via extends from the surface of the first encapsulant into the carrier.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: November 8, 2022
    Assignee: ADVANCED SEMICONDUCTORE ENGINEERING KOREA, INC.
    Inventors: Seokbong Kim, Eunshim Lee
  • Patent number: 11489060
    Abstract: The present application provides a semiconductor device with an air gate spacer for reducing parasitic capacitance and a method for manufacturing the semiconductor device. The semiconductor device includes a stacking structure, a first sidewall spacer and a second sidewall spacer. The stacking structure stands on a semiconductor substrate. The first and second sidewall spacers cover a sidewall of the stacking structure. An air gap is sealed between the first and second sidewall spacers. A top end of the air gap is substantially aligned with top ends of the first and second sidewall spacers. A top portion of the air gap is tapered toward a top end of the air gap.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: November 1, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11482555
    Abstract: A semiconductor device includes a support body including a mount region, a semiconductor chip disposed on the mount region with a predetermined distance therebetween, a bump disposed between the support body and the semiconductor chip, a wall portion disposed between the support body and the semiconductor chip along a part of an outer edge of the semiconductor chip, and an underfill resin layer disposed between the support body and the semiconductor chip. The underfill resin layer covers an outer side surface of the wall portion.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: October 25, 2022
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Shin-ichiro Takagi, Yasuhito Yoneta, Masaharu Muramatsu, Nao Inoue, Hirokazu Yamamoto, Shinichi Nakata, Takuo Koyama
  • Patent number: 11482668
    Abstract: In some embodiments, the present disclosure relates to method of forming an integrated chip. The method includes forming a bottom electrode structure over one or more interconnect layers disposed within one or more stacked inter-level dielectric (ILD) layers over a substrate. The bottom electrode structure has an upper surface having a noble metal. A diffusion barrier film is formed over the bottom electrode structure. A data storage film is formed onto the diffusion barrier film, and a top electrode structure is over the data storage film. The top electrode structure, the data storage film, the diffusion barrier film, and the bottom electrode structure are patterned to define a memory device.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: October 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hai-Dang Trinh, Chii-Ming Wu, Hsing-Lien Lin, Fa-Shen Jiang
  • Patent number: 11482689
    Abstract: Embodiments of the present disclosure provide a packaging method, an electronic device, and a packaging apparatus. The packaging method includes: providing a first substrate and a second substrate; and cell-assembling the first substrate and the second substrate to sandwich a filling glue between the first substrate and the second substrate to form a packaging structure, the filling glue is mixed with electrophoretic liquid encapsulated by a capsule, and the electrophoretic liquid includes an electrophoretic particle; in a process of cell-assembling the first substrate and the second substrate, applying an electric field to control the electrophoretic particle to move directionally to deform the capsule.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: October 25, 2022
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventors: Mengmeng Lu, Sha Feng, Bo Zhou, Yongzhi Song