Abstract: A digital filter structure and related method of digital filtering are presented. The digital filter structure is arranged to receive one or more clocked input signals having a first clock rate, and which is driven at a second clock rate higher than said first clock rate. The digital filter structure has a plurality of delay elements and multiplexing circuitry arranged to selectively engage the delay elements such that, at every clock cycle of the digital filter structure, a filter operation is performed on a different stream of data. The disclosure can be applied in many different contexts. One particular implementation example is that of an adaptive noise cancellation (ANC) system using sigma-delta infinite impulse response filters. In this context the present disclosure minimizes latency and hardware implementation area by requiring only one filtering circuit for multiple channels of data to be filtered.

Abstract: Apparatuses, methods of operating apparatuses, and corresponding computer programs are disclosed. In the apparatuses input circuitry receives input data comprising at least one data element and shift circuitry generates, for each data element of the input data, a bit-map giving a one-hot encoding representation of the data element, wherein a position of a set bit in the bit-map is dependent on the data element. Summation circuitry generates a position summation value for each position in the bit-map, wherein each position summation value is a sum across all bit-maps generated by the shift circuitry from the input data. Maximum identification circuitry determines at least one largest position summation value generated by the summation circuitry and output circuitry to generate an indication of at least one data element corresponding to the at least one largest position summation value. The statistical mode of the data elements in the input data is thereby efficiently determined.

Abstract: A resampling method based on window function for flexible sampling rate conversion in broadband frequency measurement devices is described. The resampling algorithm can satisfy the requirements of different sampling rates. The frequency responses of the filter in the resampling model based on the Farrow structure are analyzed, and the design criterion of the filter in resampling model is considered. A fractional delay filter design model based on window function method is described. A fractional delay filter matrix, which is expressed by polynomial form, is constructed. Then the expression related to subfilter coefficients is obtained and subfilter coefficients are solved for by the least square method.

Abstract: The present disclosure describes a computer using a combination of analogue and digital components/elements used in a cohesive manner. Depending on the signals and data the computer manipulates, the analog processing elements and digital processing elements can be used separately, independently or in combination to optimize the computational results and the performance of the computer.

Abstract: Embodiments of the present disclosure pertain to switch matrix circuit including a data permutation circuit. In one embodiment, the switch matrix comprises a plurality of adjacent switching blocks configured along a first axis, wherein the plurality of adjacent switching blocks each receive data and switch control settings along a second axis. The switch matrix includes a permutation circuit comprising, in each switching block, a plurality of switching stages spanning a plurality of adjacent switching blocks and at least one switching stage that does not span to adjacent switching blocks. The permutation circuit receives data in a first pattern and outputs the data in a second pattern. The data permutation performed by the switching stages is based on the particular switch control settings received in the adjacent switching blocks along the second axis.

Abstract: A method includes receiving an input data at a FP arithmetic operating unit configured to perform a FP arithmetic operation on the input data. The method further includes determining whether the received input data generates a FP hardware exception responsive to the FP arithmetic operation on the input data, wherein the determining occurs prior to performing the FP arithmetic operation. The method also includes converting a value of the received input data to a modified value responsive to the determining that the received input data generates the FP hardware exception, wherein the converting eliminates generation of the FP hardware exception responsive to the FP arithmetic operation on the input data.

Abstract: A system includes a memory and a node. The memory stores first and second log string correlithm objects. The node aligns the first and second log string correlithm objects such that a sub-string correlithm object from the first log string correlithm object associated with the logarithmic value of ten aligns with a sub-string correlithm object from the second log string correlithm object representing the logarithmic value of one. The node receives a first real-world numerical value and identifies a first sub-string correlithm object from the first log string correlithm object that corresponds to the first real-world numerical value. The node determines which sub-string correlithm object from the second log string correlithm object aligns in n-dimensional space with the first sub-string correlithm object from the first log string correlithm object, and outputs the determined sub-string correlithm object.

Abstract: A circuit for performing multiply/accumulate operations evaluates a type of each value of a pair of input values. Signed values are split into sign and magnitude. One or more pairs of arguments are input to a multiplier such that the arguments have fewer bits than the magnitude of signed values or unsigned values. This may include splitting input values into multiple arguments and inputting multiple pairs of arguments to the multiplier for a single pair of input values.

Abstract: A signal density modulation (SDM) encoder includes a first subtractor, a sigma circuit and a multi-bit quantizer. The first subtractor is used for receiving an input signal. The sigma circuit is coupled to the first subtractor. The multi-bit quantizer, coupled to the first subtractor and the sigma circuit, is configured to generate an output signal. The sigma circuit or the multi-bit quantizer produces a first feedback signal to the first subtractor. The first subtractor performs a subtraction operation according to the first feedback signal and the input signal, and generates a delta signal. The sigma circuit performs an operation on the delta signal, such that the SDM encoder has a noise transfer function having a high pass filtering effect. The noise transfer function is a ratio of a quantization error brought by the multi-bit quantizer with respect to the input signal. The output signal has more than two levels.

Abstract: A processor-implemented method of processing neural network data includes: setting first limit data by performing a first operation based on first input data and weight data generated from weights included in a filter; comparing the first limit data with an intermediate result of a second operation performed based on second input data and the weight data; and determining whether to perform a subsequent second operation based on a result of the comparing.

Abstract: The present invention relates to a method for generating a prime number and using it in a cryptographic application, comprising the steps of: a) determining at least one binary base B with a small size b=log2(B) bits and for each determined base B at least one small prime pi such that B mod pi=1, with i an integer, b) selecting a prime candidate YP, c) decomposing the selected prime candidate YP in a base B selected among said determined binary bases : YP=?yjBid) computing a residue yPB from the candidate YP for said selected base such that yPB=?yje) testing if said computed residue yPB is divisible by one small prime pi selected among said determined small primes for said selected base B, f) while said computed residue yPB is not divisible by said selected small prime, iteratively repeating above step e) until tests performed at step e) prove that said computed residue yPB is not divisible by any of said determined small primes for said selected base B, g) when said computed residue yPB is not divisible by a

Abstract: An example apparatus includes a matrix processor in circuit with a probability generator to determine a first matrix representative of element-wise multiplication between a constraint matrix and a first transpose matrix of the estimated demographic impression distribution, the constraint matrix based on the reference demographic impression distribution and determine a second matrix by multiplying the first matrix with a second transpose matrix of the constraint matrix. The apparatus further includes an error determiner in circuit with the matrix processor, the error determiner to determine an error indicator value based on the second matrix, the error indicator value indicative of an error associated with the estimated demographic impression distribution, and a probability generator to generate, in response to the error indicator value satisfying a threshold, an accuracy-improved demographic impression distribution.

Abstract: Methods, systems, and apparatus for quantum phase estimation. In one aspect, an apparatus includes a quantum circuit comprising a first quantum register comprising at least one ancilla qubit, quantum gates, comprising at least (i) two Hadamard gates, (ii) a phase gate, (iii) a unitary operator, and (iv) a measurement operator, a second quantum register comprising one or more qubits, wherein the second quantum register is prepared in an arbitrary quantum state that is not an eigenstate of the unitary operator; and a phase learning system, configured to perform phase estimation experiments on the quantum circuit, comprising repeatedly measuring the state of an ancilla qubit for each phase estimation experiment to determine an expectation value of the state of the ancilla qubit and learn phases of the eigenvalues of the unitary operator.

Abstract: An aspect includes an apparatus for evaluating a mathematical function at an input value. The apparatus includes a selector for selecting a mathematical function, an input for a value at which to evaluate the function, an identifier for identifying an interval containing the input value. The interval is described by at least one polynomial function. At least one control point representing the polynomial function is retrieved from at least one look up table, and the polynomial function can be derived from the control points. The function is evaluated at the input value and an output of the evaluation is used as a value of the function at that input value.

Abstract: An oversampling channelizer for processing overlapping data that includes a data storage unit, coupled to a data line that receives data values. The data storage unit includes a plurality of lanes, wherein each of the plurality of lanes includes dedicated memory locations and wires that store and transmit data values for a data vector of a data frame, and that store and transmit additional data values for a subsequent data vector of a subsequent data frame that includes a plurality of the data values from the data vector in the data frame. The oversampling channelizer includes a coefficient storage unit that stores a plurality of coefficient vectors for a plurality of coefficient frames. The oversampling channelizer includes a computation unit that computes a dot product of the data values for the data vectors of the data frame with coefficient values for coefficient vectors of a coefficient frame selected by a coefficient storage unit.

Abstract: Disclosed herein is a novel multi-way merge network, referred to herein as a Hybrid Comparison Look Ahead Merge (HCLAM), which incurs significantly less resource consumption as scaled to handle larger problems. In addition, a parallelization scheme is disclosed, referred to herein as Parallelization by Radix Pre-sorter (PRaP), which enables an increase in streaming throughput of the merge network. Furthermore, high performance reduction scheme is disclosed to achieve full throughput.

Abstract: Some embodiments provide a program. The program receives from a client device a sourcing request specifying a plurality of variables comprising set of sources, a set of items, and a set of quantities associated with the items. The program further receives a set of offers from the set of sources. Each offer in the set of offers specifies an item in set of items, a price associated with the item, and a quantity associated with the item. The program also receives a selection of a set of defined scenarios for the sourcing event and the set of offers. The program further generates a set of linear programming models based on the set of defined scenarios the sourcing and the set of offers. The program also instructs solvers to solve the liner programming models.

Abstract: A microprocessor system comprises a matrix computational unit and a control unit. The matrix computational unit includes one or more processing elements. The control unit is configured to provide a matrix processor instruction to the matrix computational unit. The matrix processor instruction specifies a floating-point operand formatted with an exponent that has been biased with a specified bias.

Abstract: The invention relates to a method for determining a value of an integer scaling in a linking of input sets to output sets, wherein the linking comprises operators, each of which has operator inputs and operator outputs that are at least partially linked to one another or to the input sets or to the output sets, by using a computer device having a processing unit, a memory unit, and an output unit. Representations of set objects are used to efficiently carry out rescaling operations within the linking, with up to infinitely large resolution sets. This procedure makes it possible to calculate resource-conserving integer scalings for a target system while taking secondary conditions into account.

Abstract: The present disclosure provides a high-speed random number generation method and device, comprising an entropy source module and an entropy sampling module. The entropy source module is an autonomous Boolean network formed by digital logic gates, the network is formed by an XNOR gate and (N?1) XOR gates, wherein the value of N is equal to 3n (n is a positive integer), and the entropy source can generate chaotic signals having wide and flat frequency spectrum. The entropy sampling module of the present disclosure is formed by D flip flops used for sampling and quantizing the chaotic signals to generate random number sequences. The random number sequences generated by the present disclosure can pass test standards (NIST and Diehard statistic tests) of random number industry and have excellent random statistic characteristics.