Abstract: A system may comprise a plurality of processing units and a scheduler configured to maintain a record for each respective processing unit. Each respective record may comprise entries which may indicate 1) how long the respective processing unit has been residing in an idle state, 2) a present power-state in which the respective processing unit resides, and 3) whether the respective processing unit is a designated default (bootstrap) processing unit. The scheduler may select one or more of the plurality of processing units according to their respective records, and assign impending instructions to be executed on the selected one or more processing units. Where additional processing units are required, the scheduler may also insert an instruction to trigger an inter-processor interrupt to transition one or more processing units out of idle-state. The scheduler may then assign some impending instructions to these one or more processing units.

Abstract: An IC (100) for communicating over a data communication bus (220) comprising a first pair of conductors including a data signal conductor (SDA) and a synchronization signal conductor (SCL), e.g. an I2C bus, is disclosed. The IC comprises a group of address pins (106a-c) for defining the bus address of the integrated circuit (100), each address pin being arranged to be coupled to a conductor from a group of conductors comprising the first pair of conductors and a second pair of conductors including a conductor for carrying a fixed high potential (Vdd) and a conductor for carrying an fixed low potential (GND).

Abstract: A system may comprise a plurality of processing units, and a control unit and monitoring unit interfacing with the processing units. The control unit may receive requests for transitioning the processing units to respective target power-states, and specify respective target HW power-states corresponding to the respective target power-states. The monitoring unit may monitor operating characteristics of the system, and determine based on operating characteristics whether to allow the processing units to transition to the respective target hardware (HW) power-states. The control unit may be configured to change the respective target HW power-state to a respective updated HW power-state for each processing units for which it is determined that transition to its respective target HW power-state should not be allowed.

Abstract: A digital data register is disclosed that provides setup and hold timing on the pre-register side, clock centering on the post-register side, and constant propagation delay time over variations in process, supply voltage and temperature (PVT) using a novel means to generate and distribute the clock signal. These features allow the register to be used in applications operating at clock frequencies in excess of 800 MHz.

Abstract: Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided that comprises a storage circuit programmable to store a routing value, and a transmission circuit. In a transmission mode of operation the transmission circuit is responsive to the routing value indicating that the data input path should be coupled to the data output path to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. Control circuitry is used to issue control signals to the crossbar cells, and during a configuration mode of operation the control circuitry re-utilizes at least one of the data output paths to program the storage circuitry of one or more of the crossbar cells.

Abstract: A method for automatically switching power states is disclosed. According to the method, when an electronic apparatus is in a power-saving state and a waking up time is reached, the electronic apparatus is switched into a working state, and when an executing time is reached, the electronic apparatus automatically executes an assigned function. After completing the assigned function, the electronic apparatus is switched back into the power-saving state for energy-saving purpose.

Abstract: Apparatus for combining powers coming from a plurality of I/O ports. Use of the apparatus to power electronic appliances that can require more power than can be delivered by a single I/O port, e.g. in order to charge more quickly energy storage means forming part of the portable electronic appliance connected to the apparatus.

Abstract: Certain aspects of a method and system for a hardware-based implementation of USB 1.1 over a high-speed link may comprise translating at a client side of a client server communication system, USB protocol messages comprising a first USB standard to corresponding encapsulated USB protocol messages, wherein the USB protocol messages comprising the first USB standard are received from a client device at the client side of the client server communication system. The translated corresponding encapsulated USB protocol messages may be communicated from the client side to a server at a server side of the client server communication system.

Abstract: A data reception apparatus includes: an oscillation circuit that multiplies or divides an oscillation signal from a CR oscillator based on a cycle setting value, and outputs a clock signal corresponding to the multiplied or divided oscillation signal; a temperature detector; a memory; a clock cycle setting element that reads the cycle setting value corresponding to the temperature from the memory, and inputs the cycle setting value into the oscillation circuit; a receiver that receives a data signal defined by the clock signal; a measurement element that measures a unit bit length of the data signal by counting the clock signal; and a correction element that corrects the cycle setting value based on a count value of the clock signal and a reference count value of a reference cycle corresponding to the unit bit length, and rewrites the cycle setting value with the corrected cycle setting value.

Abstract: A method and apparatus are provided for implementing connection management in SAS expander devices. SAS expanders are commonly used within a SAS network topology to allow multiple disk drives to connect to multiple host devices. The method and apparatus provides arbitration of connection requests to be setup or removed among multiple end devices and expander devices so as to increase system performance and reduce hardware cost in a standard compliant manner.

Abstract: An electronic device, includes a USB interface, a processing unit, a master-slave select triggering circuit, a controlling unit, a selection circuit and a switching circuit. The master-slave selection triggering circuit including an input port, a first output port and a second output port. The master-slave select triggering circuit is used to detect the type of external electronic devices connected to the USB interface, if the external electronic device is a master device, the first and second output port output a slave triggering signal, the controlling unit switches off the switching circuit t and the selection circuit selects the processing unit into slave mode; if the external electronic device is the slave device, the first and second output port output a master triggering signal, the controlling unit switches on the switching circuit and the selection circuit select the processing unit into master mode.

Abstract: Methods, apparatus, and products are disclosed for reducing power consumption while synchronizing a plurality of compute nodes during execution of a parallel application that include: beginning, by each compute node, performance of a blocking operation specified by the parallel application, each compute node beginning the blocking operation asynchronously with respect to the other compute nodes; reducing, for each compute node, power to one or more hardware components of that compute node in response to that compute node beginning the performance of the blocking operation; and restoring, for each compute node, the power to the hardware components having power reduced in response to all of the compute nodes beginning the performance of the blocking operation.

Abstract: Described is a method of providing the communication between two or more control units of a control apparatus that controls at least one electronic device which comprises two or more peripheral units. The method is characterized by comprising the steps of: providing a common bus; connecting said two or more control units by way of said common bus; controlling, through each control unit, at least one peripheral unit of the device to provide data necessary for the operation of the peripheral unit and to detect possible data variation of said peripheral unit; and providing for a master controller connected to the common bus, and further by the steps, carried out by each of said control units, of submitting to said master controller, information related to data consumed and to data provided by the peripheral units controlled by said control units; and sending a message over the bus whenever at least one of the data provided by the peripheral units controlled by said control units changes.

Abstract: A method for accessing serial peripheral interface (SPI) slave devices using an SPI control device determines an SPI slave device to be operated, sets an operation type of the determined SPI slave device, and further sets a clock rate, a clock phase, and a clock polarity of the determined SPI slave device. The method further generates a clock signal according to the clock rate, the clock phase, and the clock polarity of the determined SPI slave device, and performs a read operation or a write operation on the determined SPI slave device according to the clock signal.

Abstract: Methods and apparatus are provided for providing a first master component with access to a first slave component while a second master component is accessing a second slave component in a system. The system may include a processor core and peripherals implemented on an integrated circuit. A slave side arbitrator corresponding to a single slave component and coupled to multiple master components can be used to provide a master component access to a slave component.

Abstract: A host module is disclosed, in which an interface is used to couple to at least an electronic device through a serial bus and comprises at least first and second ports. A detection unit reports that one of the first and second ports is enabled and the other is not enabled to a serial bus host driver and enables the interface to perform data transmission with the electronic device connected to the first and second ports through two parallel transmission channels of the serial bus, when the first and second ports are both connected to the same electronic device through the serial bus.

Abstract: The invention relates to a communications method of communicating states from an activation unit to a receiver via a communications bus, wherein the state may be activation/deactivation of an activation unit, and wherein the state is communicated to the receiver via a serial data stream timed by a clock signal, said data stream transmitting data packets which comprise an identification part and a data pare wherein: ? the identification part comprises a plurality of bits which identify which activation units the data packet concerns, and ? the data part comprises a plurality of bits which individually identify the state of an activation unit. The invention also relates to a system based on the communications method and comprising an activation unit and a receiver. In addition, the invention relates to an activation unit and a receiver.

Abstract: An abnormal status detecting method of interrupt pins is provided. In the invention, an advanced configuration and power interface (ACPI) table is looked up for obtaining an interrupt status bit of each interrupt pin in a computer system. Afterwards, the interrupt status bit is continuously checked whether it is maintained at a specific value during a fixed time. When the interrupt status bit of one of the interrupt pins is maintained at the specific value during the fixed time, the interrupt pin is determined to be abnormal.

Abstract: A processing system includes a plurality of first circuit modules. A plurality of second circuit modules are coupled to an RF data bus via a 60 GHz communications. The RF data bus receives first data from at least one of the plurality of first circuit modules, and transmits the first data via 60 GHz communications to at least one of the plurality of second circuit modules.

Abstract: A medical device system includes a portable medical device and a docking unit on which the medical device can be removably mounted. The docking unit is configured to communicate with a controller of the medical device when the medical device is mounted on the docking unit to instruct the controller to execute a selected program.