Abstract: Exemplary embodiments of methods and apparatuses to manage a power of a data processing system are described. One or more constraint parameters of a system are monitored. The data processing system is forced into an idle state for a first portion of a time while allowed to operate for a second portion of the time based on the one or more constraint parameters, wherein the system is forced into the idle state in response to comparing a target idle time to an actual idle time. The target idle time of the system is determined, in one embodiment, based on the one or more constraint parameters. The actual idle time of the system may be monitored to take into account interrupts which disrupt an idle time and idle times resulting from no software instructions to execute. The system may be allowed to operate based on comparisons of the target idle time and the actual idle time.

Abstract: A processing system includes a plurality of first circuit modules. A plurality of second circuit modules are coupled to an RF data bus via intra-device RF communications. The RF data bus receives first data from at least one of the plurality of first circuit modules, and transmits the first data via intra-device RF communications to at least one of the plurality of second circuit modules.

Abstract: In the novel device and the novel method the data to be transmitted is transmitted in units together with information that is required or useful for the transmission and/or the use of the data. At least some of the units comprise at least one region which defines a time slot within which freely selectable devices can output onto the bus data representing freely selectable information at freely selectable points in time.

Abstract: A new simple serial interface method and device based on this method, which reduces the complexity of the existing universal serial bus (USB) interface, and allows fast and efficient data exchange, and quick development of hardware and software for this device. The method allows equal exchange of information between 2 participants wherein: each participant can initiate sending of information, the data exchange can occur at any time, with no wait or a reference in a ‘frame’. The device based on the method implemented as: separate UTMI or wireless interface chip and separate control chip, single chip which includes UTMI or wireless part, and control part, special mode included in the existing—USB host, USB device, USB OTG chips.

Abstract: A system and a method are disclosed for allowing a host device to communicate with an accessory device using a lightweight communications protocol. A communications link is first established between the connected accessory and host device. The host device sends a request for a register map file (RMF) to the accessory device. A RMF identifies registers for elements of the accessory device. The accessory device sends the RMF to host device, responsive to the request and the host device maps the RMF to interface with a higher level language such as C++ or JavaScript, allowing the host to act on the register mapping. Such interaction can be handled at the driver layer of an operating system, the application framework layer or the application layer. This permits both a layered service model and a fine-grant access at the application layer of the host device.

Abstract: A device has first circuitry and also second circuitry that includes an interface and command ports that can each receive commands from the first circuitry, each command requesting an information transfer through the interface. A technique relating to the device involves dynamically enabling and disabling at least one of the command ports under control of the first circuitry, and using a priority list specifying an order of priority for a group of the command ports to identify and cause a command to be accepted from the command port of highest priority that contains a command and is currently enabled.

Abstract: Methods, apparatus, and products are disclosed for reducing power consumption during execution of an application on a plurality of compute nodes that include: executing, by each compute node, an application, the application including power consumption directives corresponding to one or more portions of the application; identifying, by each compute node, the power consumption directives included within the application during execution of the portions of the application corresponding to those identified power consumption directives; and reducing power, by each compute node, to one or more components of that compute node according to the identified power consumption directives during execution of the portions of the application corresponding to those identified power consumption directives.

Abstract: The advanced management module services in a data processing system are configured to determine the system load and provide an input to the early power off warning detection logic that evaluates the power system state to detect a condition when power resources are insufficient to maintain the write caching storage system power within defined acceptable limits. The early power off warning detection logic generates a notification based on the system load and the available power supply resources to maintain maximum availability and reliability characteristics.

Abstract: Methods and apparatus are provided for virtualizing resources including peripheral components and peripheral interfaces. Peripheral component such as hardware accelerators and peripheral interfaces such as port adapters are offloaded from individual servers onto a resource virtualization switch. Multiple servers are connected to the resource virtualization switch over an I/O bus fabric such as PCI Express or PCI-AS. The resource virtualization switch allows efficient access, sharing, management, and allocation of resources.

Abstract: A quick port-switching method and associated apparatus are provided. A quick port-switching display control circuit includes a display controller, a first TMDS port, a second TMDS port and an analog video port. The display controller has a first GPIO pin and a second GPIO pin. The first TMDS port, second TMDS port and analog video port are coupled to the display controller for receiving a first TMDS input, a second TMDS input and an analog video signal, respectively. The first TMDS input and second TMDS input include a first hot-plugging signal and a second hot-plugging signal to be received by the first GPIO pin and second GPIO pin, respectively. The display controller determines whether the first TMDS input is valid by detecting whether the first hot-plugging signal is asserted, and determines whether the second TMDS input is valid by detecting whether the second hot-plugging signal is asserted.

Abstract: A two reference clock architected redriver includes an inbound elastic buffer and an outbound elastic buffer. Data transmitted to and received from a North Bridge uses a common reference clock architecture. Data transmitted to and received from an external blade uses a separate reference clock architecture. The inbound elastic buffer includes an inbound elastic buffer recovered clock domain, an inbound elastic buffer common reference clock domain, and an inbound decoder/descrambler, an inbound scrambler/encoder, and inbound liner shift registers. The outbound elastic buffer includes an outbound elastic buffer common reference clock domain, an outbound elastic buffer low jitter clock domain, and an outbound decoder/descrambler, an outbound scrambler/encoder, and outbound liner shift register.

Abstract: An apparatus for processing a PCI Express protocol, includes: a PCI Express transaction layer reception unit for transmitting status information, and performing a data writing operation; a PCI Express data link layer transmission unit for creating a flow control packet, transmitting the flow control packet to a PCI Express physical layer, and transmitting an integrity acknowledgement packet to the PCI Express physical layer; and a PCI Express physical layer for transmitting the flow control packet and the integrity acknowledgement packet to an upstream device, and transmitting the writing request packet to a PCI Express data link layer reception unit. Further, the apparatus includes a PCI Express data link layer reception unit for transmitting the writing request packet to the PCI Express transaction layer reception unit, and transmitting the integrity acknowledgement packet to the PCI Express data link layer transmission unit and a PCI Express transaction layer reception unit.

Abstract: Methods, apparatus, and products are disclosed for reducing power consumption while synchronizing a plurality of compute nodes during execution of a parallel application that include: beginning, by each compute node, performance of a blocking operation specified by the parallel application, each compute node beginning the blocking operation asynchronously with respect to the other compute nodes; reducing, for each compute node, power to one or more hardware components of that compute node in response to that compute node beginning the performance of the blocking operation; and restoring, for each compute node, the power to the hardware components having power reduced in response to all of the compute nodes beginning the performance of the blocking operation.

Abstract: A power management controller (PMC) that interfaces with a processor comprising one or more cores. The PMC may be configured to communicate with each respective core, such that microcode executed by the respective processor core may recognize when a request is made to transition the respective core to a target power-state. For each respective core, the state monitor may monitor active-state residency, non-active-state residency, Direct Memory Access (DMA) transfer activity associated with the respective core, Input/Output (I/O) processes associated with the respective core, and the value of a timer-tick (TT) interval associated with the respective core. The status monitor may derive respective status information for the respective core based on the monitoring and indicate whether the respective core should be allowed to transition to the corresponding target power-state. The PMC may transition the respective processor core to the corresponding target power-state accordingly.

Abstract: A method and apparatus for data transfer includes receiving a first data packet across a first bi-directional bus and receiving a second data packet across a second bi-directional bus. Next, the first data packet is written to a first register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is written to a second register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is then transferred across the first bi-directional bus and the first data packet is transferred across the second bi-directional bus, thereby providing data transfer across a plurality of bi-directional buses and providing for data to be transferred across those buses to be stored at an intermediate register so that the data may be transferred in the next clock cycle, overcoming any latency requirements.

Abstract: A slave device may receive commands from a host device communicatively coupled to the slave device, via a secure interface configured between the slave device and the host device over that coupling. An integrated memory within the slave device may be configured into a plurality of memory portions or regions based on the received commands. The memory regions may be utilized during operations associated with authentication of subsequent commands from the host device. A first memory region may enable storage of encrypted host commands and data. A second region may enable storage of decrypted host commands and data. A third region may enable storage of internal variables and/or intermediate results from operations performed by the slave device. Another region may comprise internal registers that enable storage of information only accessible to the slave device. Access to some of the memory regions may be controlled and/or restricted by the slave device.

Abstract: In a hierarchical bus structure employing a fixed-priority bus access arbitration scheme, accurate arbitration of bus access requests can be carried out even in situations where priority levels are updated according to a system operation mode. In each of a plurality of superordinate hierarchical bus circuits, access requests from respective bus masters included in each corresponding bus master group are arbitrated according to priority levels assigned thereto, and based on the result of the arbitration, a priority communication signal PRA/PRB indicating a priority level of each access-request-permitted bus master is fed to a subordinate bus controller. In a subordinate hierarchical bus circuit, under control of the subordinate bus controller, access request arbitration is carried out according to the priority communication signal PRA/PRB to select a superordinate hierarchical bus circuit or bus master having the highest priority level.

Abstract: A network adaptor is disclosed that uses Power over Ethernet (PoE) protocols to derive power from an Ethernet port and provide the derived power to a field device. The network adapter communicates analog data with the field device and converts the analog data to digital data using an analog to digital converter before transmitting the digital data through the Ethernet port to a central office. The network adapter is uniquely assigned to the field device allowing an IP address to be assigned to the network adapter/field device system which may be accessed using IP protocols from any suitable browser.

Abstract: A power saving mode is provided. A method for entering a power saving mode of a terminal includes a first operation for starting a first timer after transmitting an idle mode request message; a second operation for, when an idle mode approval message is not received until the first timer expires, checking whether a number of retransmissions of the idle mode request message exceeds a number of allowed retransmissions of the idle mode request message; a third operation for, when the number of the retransmissions of the idle mode request message exceeds the number of the allowed retransmissions of the idle mode request message, increasing a number of idle mode entry failures; and a fourth operation for, when the increased number of the idle mode entry failures is greater than N times, entering a power saving mode which powers off a modem.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.