Abstract: The embodiments of the present disclosure provide an organic light emitting device including a first electrode, a second electrode, and an organic functional layer, wherein the organic functional layer includes a first doped layer fabricated in a first process, a second doped layer fabricated in a second process, and an auxiliary layer formed between the first doped layer and the second doped layer, wherein the auxiliary layer is used to improve the performance of the first doped layer. The embodiments of the present disclosure further provide a method for fabricating the organic light emitting device. The embodiments of the present disclosure also provide a display apparatus including the organic light emitting device.

Abstract: An embodiment provides: a method for manufacturing a silicon carbide epi wafer, the method comprising the steps of preparing a wafer, applying a reaction gas to the wafer, heating the reaction gas to generate an intermediate compound, and forming a silicon carbide epi layer on the wafer using the generated intermediate compound, wherein the reaction gas contains a plurality of hydrocarbon compounds; and a silicon carbide epi wafer comprising a silicon carbide epi layer formed by a reaction gas containing a plurality of hydrocarbon compounds, wherein the C/Si value of the silicon carbide epi layer is uniform on the wafer, and thus the uniformity of the silicon carbide epi layer on the wafer can be improved.

Abstract: A trench has first to third side surfaces respectively constituted of first to third semiconductor layers. A first side wall portion included in a first insulating film has first to third regions respectively located on the first to third side surfaces. A second insulating film has a second side wall portion located on the first side wall portion. The second side wall portion has one end and the other end, the one end being connected to the second bottom portion of the second insulating film, the other end being located on one of the first and second regions, the other end being separated from the third region.

Abstract: A method of fabricating a semiconductor device includes forming first and second active patterns on first and second regions, respectively, of a substrate, forming first and second gate structures on the first and second active patterns, respectively, forming a coating layer to cover the first and second gate structures and the first and second active patterns, and forming a first recess region in the first active pattern between the first gate structures and a second recess region in the second active pattern between the second gate structures.

Abstract: A semiconductor structure includes a substrate, a first semiconductor fin, a second semiconductor fin, and a first lightly-doped drain (LDD) region. The first semiconductor fin is disposed on the substrate. The first semiconductor fin has a top surface and sidewalls. The second semiconductor fin is disposed on the substrate. The first semiconductor fin and the second semiconductor fin are separated from each other at a nanoscale distance. The first lightly-doped drain (LDD) region is disposed at least in the top surface and the sidewalls of the first semiconductor fin.

Abstract: Semiconductor devices may include a semiconductor substrate comprising at least one of transistors and capacitors may be located at an active surface of the semiconductor substrate. An imperforate dielectric material may be located on the active surface, the imperforate dielectric material covering the at least one of transistors and the capacitors. Electrically conductive material in contact openings may be electrically connected to the at least one of transistors and capacitors and extend to a back side surface of the semiconductor substrate. Laterally extending conductive elements may extend over the back side surface of the semiconductor substrate and may be electrically connected to the conductive material in the contact openings.

Abstract: A semiconductor-on-insulator wafer includes a support substrate, an electrically insulating layer over the support substrate and a semiconductor layer over the electrically insulating layer. A semiconductor structure includes a transistor. The transistor includes an electrically insulating layer including a piezoelectric material over a support substrate, a semiconductor layer over the electrically insulating layer, a source region, a channel region and a drain region in the semiconductor layer, a gate structure over the channel region, a first electrode and a second electrode. The first electrode and the second electrode are provided at laterally opposite sides of the electrically insulating layer. The first and second electrodes are electrically insulated from the semiconductor layer and configured for applying a voltage to the piezoelectric material of the electrically insulating layer. The piezoelectric material creates a strain at least in the channel region in response to the voltage applied thereto.

Abstract: A thin film transistor and a manufacturing method thereof, an array substrate and a display device are provided. The method includes forming a gate electrode, a gate insulating layer, a metal oxide semiconductor (MOS) active layer, a source electrode and a drain electrode on a substrate. The MOS active layer includes forming a pattern layer of indium oxide series binary metal oxide including a first pattern directly contacting with the source electrode and the drain electrode. An insulating layer formed over the source electrode and the drain electrode acts as a protection layer, the pattern layer of indium oxide series binary metal oxide is implanted with metal doping ions by using an ion implanting process, and is annealed, so that the indium oxide series binary metal oxide of the third pattern is converted into the indium oxide series multiple metal oxide to form the MOS active layer.

Abstract: A pad structure including a plurality of material pairs and a plurality of pads is provided. The material pairs are stacked on a substrate to form a stair step structure. A stair step of the stair step structure includes one of material pairs. Each of the material pairs includes a conductive layer and a dielectric layer on the conductive layer. Each of the pads is embedded in one stair step of the stair step structure and exposed by the dielectric layer corresponding to the one stair step and another stair step above the one stair step. A thickness of one of the pads is greater than a thickness of one of the conductive layers.

Abstract: A complementary metal-oxide semiconductor (CMOS) device and a method of fabricating a CMOS device are described. The method includes forming an interfacial layer in a trench on a substrate in both a p-channel field effect transistor (pFET) area of the CMOS device and an n-channel FET (nFET) area of the CMOS device, depositing a high-k dielectric on the interfacial layer in both the pFET area and the nFET area, selectively forming a first metal layer on the high-k dielectric in only the pFET area, and depositing a second metal layer on the first metal layer in the pFET area and on the high-k dielectric in the nFET area. The method also includes performing an anneal that increases a thickness of the interfacial layer in only the pFET area.

Abstract: A semiconductor device has a first semiconductor die with a base material. A covering layer is formed over a surface of the base material. The covering layer can be made of an insulating material or metal. A trench is formed in the surface of the base material. The covering layer extends into the trench to provide the cantilevered protrusion of the covering layer. A portion of the base material is removed by plasma etching to form a cantilevered protrusion extending beyond an edge of the base material. The cantilevered protrusion can be formed by removing the base material to the covering layer, or the cantilevered protrusion can be formed within the base material under the covering layer. A second semiconductor die is disposed partially under the cantilevered protrusion. An interconnect structure is formed between the cantilevered protrusion and second semiconductor die.

Abstract: A light emitting element includes a substrate; a plurality of semiconductor light emitting cells; a plurality of light reflective electrodes; a first insulation layer that continuously covers lateral surfaces of the semiconductor light emitting cells, spaces between the semiconductor light emitting cells, lateral surfaces of the light reflective electrodes, and a portion of upper surfaces of the light reflective electrodes; a plurality of wiring electrodes, and cover the lateral surfaces of the semiconductor light emitting cells and the spaces between the semiconductor light emitting cells via the first insulation layer; and a light reflective metal layer that covers the lateral surfaces of at least two adjacent ones of the semiconductor light emitting cells and the space between said at least two semiconductor light emitting cells, via the first insulation layer.

Abstract: A manufacturing method for an array substrate is provided in the present invention. The method comprises: forming a Poly-Silicon layer on a glass substrate; forming heavily doped regions by performing heavily doping and activation process at both sides of the Poly-Silicon layer; forming a source/a drain of a first metal layer growing on the heavily doped region; forming a gate of both a gate insulator and a second metal layer growing sequentially on the Poly-Silicon layer, wherein, a material of the second metal layer is aluminum. The activation technology process can be improved in the present invention to reduce RC delay in metal wires of product and then further to achieve large sizes for products.

Abstract: Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.

Abstract: A sintering paste includes solvent and nanomicrocrystallite (NMC) particles. Each NMC particle is a single crystallite having at least one dimension in the range of 1 nm to 100 nm and at least one dimension in the range of 0.1 ?m to 1000 ?m. The sintering paste may be used in a pressureless sintering process to form a low porosity joint having high bond strength, high electrical and thermal conductivity, and high thermal stability.

Abstract: A method for forming a protecting layer includes determining an expected concentration of metal ions in a dielectric layer. The method also includes determining a thickness of the protecting layer based on the expected concentration of metal ions. The method also includes forming the protecting layer at the determined thickness and in contact with the dielectric layer. The protecting layer can include at least one of silicon doped nitride, carbon nitride, silicon nitride, or silicon carbon.

Abstract: There is provided an imaging device that includes photovoltaic type pixels that have photoelectric conversion regions generating photovoltaic power for each pixel depending on irradiation light; and an element isolation region that is provided between the photoelectric conversion regions of adjacent pixels and in a state of substantially surrounding the photoelectric conversion region.

Abstract: A flow sensor structure seals the surface of an electric control circuit and part of a semiconductor device via a manufacturing method that prevents occurrence of flash or chip crack when clamping the semiconductor device via a mold. The flow sensor structure includes a semiconductor device having an air flow sensing unit and a diaphragm, and a board or lead frame having an electric control circuit for controlling the semiconductor device, wherein a surface of the electric control circuit and part of a surface of the semiconductor device is covered with resin while having the air flow sensing unit portion exposed. The flow sensor structure may include surfaces of a resin mold, a board or a pre-mold component surrounding the semiconductor device that are continuously not in contact with three walls of the semiconductor device orthogonal to a side on which the air flow sensing unit portion is disposed.

Abstract: An example system includes a processing circuit coupled to a memory system and an interface coupled between the processing circuit and a device. The memory system includes a resistive memory array comprising multiple memory structures. Each memory structure comprises a resistive memory cell and is associated with a P-I-N diode. The processing circuit is to access the resistive memory array responsive to a signal received from the device via the interface.

Abstract: Techniques related to III-N transistors having self aligned gates, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a polarization layer between a raised source and a raised drain, a gate between the source and drain and over the polarization layer, and lateral epitaxial overgrowths over the source and drain and having and opening therebetween such that at least a portion of the gate adjacent to the polarization layer is aligned with the opening.