Abstract: A semiconductor device and a method of manufacturing the semiconductor device are included. The method of manufacturing the semiconductor device includes forming a hafnium oxide layer on a substrate and crystallizing the hafnium oxide layer by using a hafnium cobalt oxide layer as a seed layer. According to the method of manufacturing the semiconductor device, a thin-film hafnium oxide layer may be easily crystallized.

Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.

Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a first surface including a plurality of conductive pads and a second surface; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate. The insulating protective layer includes at least an opening for exposing at least one of the conductive pads, and the at least the passive component is directly provided on the conductive pad exposed from the opening.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device of the present disclosure includes a first fin including a first source/drain region, a second fin including a second source/drain region, a first isolation layer disposed between the first source/drain region and the second source/drain region, and a second isolation layer disposed over the first isolation layer. A first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region. A portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer.

Abstract: An organic electroluminescence (EL) display panel includes a substrate; first electrodes spaced away from each other and arrayed in rows and columns above the substrate; light-emitting layers including organic light-emitting material and disposed above the first electrodes; a second electrode disposed above the light-emitting layers; a first protection layer including resin and disposed above the second electrode but not within an auxiliary region which, in plan view, extends in a column direction between ones of the first electrodes that are adjacent in a row direction across the substrate; a second protection layer including inorganic material and disposed above the first protection layer and the second electrode; and an auxiliary electrode layer extending in the column direction within the auxiliary region and electrically connecting to the second electrode through a contact opening in the first protection layer within the auxiliary region.

Abstract: An organic light emitting display device includes a substrate, a first semiconductor element, a second semiconductor element, an insulation layer structure, and a light emitting structure. The substrate has a first region and a second region that is adjacent to the first region. The insulation layer structure is disposed between a second gate electrode and a second active layer of the second semiconductor element. The insulation layer structure includes a first insulation layer having a first etching rate, a second insulation layer disposed on the first insulation layer and having a second etching rate that is greater than the first etching rate, and a third insulation layer disposed on the second insulation layer and having a third etching rate that is less than the second etching rate in a same etching process. The light emitting structure is disposed on the insulation layer structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a source/drain structure adjacent to the gate stack. The semiconductor device structure also includes a cap element over the source/drain structure. The cap element has a first top plane and the source/drain structure has a second top plane. The first top plane of the cap element is wider than the second top plane of the source/drain structure. A surface orientation of the first top plane of the cap element and a surface orientation of a side surface of the cap element are different from each other.

Abstract: Techniques related to laser lift-off masks are disclosed. In some embodiments, masking material is applied to a substrate that is attached to a plurality of semiconductor device sets. More specifically, the masking material is applied to one or more regions of the substrate between the semiconductor device sets. When the semiconductor device sets are embedded in a filling material, the masking material may be situated between the substrate and the filling material. Thus, transmitting light through the substrate toward the semiconductor device sets causes the substrate to become detached from the semiconductor device sets. However, the light is at least partially occluded by the masking material.

Abstract: A high detectivity infrared photodetector is provided. An infrared photodetector 10 includes n-type semiconductor layers 3 and 5 and a photoelectric conversion layer 4. The photoelectric conversion layer 4 includes quantum dots 411, a barrier layer 42, and a single-sided barrier layer 43. The single-sided barrier layer 43 is inserted between the barrier layer 42 and the n-type semiconductor layer 5 and has a wider band gap than does the barrier layer 42. Letting y be an energy level difference between the bottom of the conduction band of the single-sided barrier layer 43 and the bottom of the conduction band of the n-type semiconductor layer 5, z be a voltage in volts applied to the photoelectric conversion layer 4, and d be a thickness in nanometers of the photoelectric conversion layer 4, the infrared photodetector 10 satisfies y?27×exp(0.64×z/(d×10000)).

Abstract: A switch device according to an embodiment of the technology includes a first electrode, a second electrode that is disposed to face the first electrode, and a switch layer that is provided between the first electrode and the second electrode. The switch layer contains a chalcogen element. The switch layer includes a first region and a second region which have different composition ratios of one or more of chalcogen elements or different types of the one or more of chalcogen elements. The first region is provided close to the first electrode. The second region is provided closer to the second electrode than the first region.

Abstract: Many of the physical properties of a silicon semiconductor have already been understood, whereas many of the physical properties of an oxide semiconductor have been still unclear. In particular, an adverse effect of an impurity on an oxide semiconductor has been still unclear. In view of the above, a structure is disclosed in which an impurity that influences electrical characteristics of a semiconductor device including an oxide semiconductor layer is prevented or is eliminated. A semiconductor device which includes a gate electrode, an oxide semiconductor layer, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer and in which the nitrogen concentration in the oxide semiconductor layer is 1×1020 atoms/cm3 or less is provided.

Abstract: Some embodiments include a semiconductor construction which has one or more openings extending into a substrate. The openings are at least partially filled with dielectric material comprising silicon, oxygen and carbon. The carbon is present to a concentration within a range of from about 3 atomic percent to about 20 atomic percent. Some embodiments include a method of providing dielectric fill across a semiconductor construction having an opening extending therein. The semiconductor construction has an upper surface proximate the opening. The method includes forming photopatternable dielectric material within the opening and across the upper surface, and exposing the photopatternable dielectric material to patterned actinic radiation.

Abstract: [Object] To provide an organic electro-luminescence device in which occurrence of failures such as local abnormal light emission and current leakage is suppressed. [Solution] An organic electro-luminescence device including: a recessed structure in which a first electrode is provided at a bottom part and a first member serves as a sidewall; a second electrode configured to cover an entire surface of the recessed structure; and an organic light emitting layer containing an evaporation material and sandwiched by the second electrode and the recessed structure. In the organic light emitting layer, a film thickness of a layer containing a leaky material is non-uniform at the bottom part of the recessed structure, and an entire film thickness of the organic light emitting layer is generally uniform at the bottom part of the recessed structure.

Abstract: The present invention relates to organic electronic devices, and more specifically to organic field effect transistors, comprising a dielectric layer that comprises a polycycloolefinic polymer and a diazirine compound.

Abstract: A semiconductor device including a first fin pattern and a second fin pattern, which are in parallel in a lengthwise direction; a first trench between the first fin pattern and the second fin pattern; a field insulating film partially filling the first trench, an upper surface of the field insulating film being lower than an upper surface of the first fin pattern and an upper surface of the second fin pattern; a spacer spaced apart from the first fin pattern and the second fin pattern, the spacer being on the field insulating film and defining a second trench, the second trench including an upper portion and an lower portion; an insulating line pattern on a sidewall of the lower portion of the second trench; and a conductive pattern filling an upper portion of the second trench and being on the insulating line pattern.

Abstract: A transient voltage suppressor (TVS) is constructed as an NPN bipolar transistor including individually optimized collector-base and emitter-base junctions both with avalanche mode breakdown. The TVS device is constructed using a base that includes a lightly doped base region bordered by a pair of more heavily doped base regions. The two more heavily doped base regions are used to form the collector-base junction and the emitter-base junction both as avalanche breakdown junctions. The lightly doped base region between the collector-base and emitter-base doping regions ensures low leakage current in the TVS device. In this manner, the TVS bipolar transistor of the present invention provides high surge protection with robust clamping while ensuring low leakage current.

Abstract: Provided are an organic light emitting diode display device and a manufacturing method thereof. The method includes: preparing a thin film transistor layer on a glass substrate; preparing an organic light emitting diode element layer on the thin film transistor layer, and preparing a barrier layer and a buffer layer on the glass substrate, wherein the barrier layer covers the OLED element layer; preparing the plurality of grooves in the barrier layer, and preparing a water absorbing material layer in the plurality of grooves. The permeability of water and oxygen is reduced for lowering the risk of breakage of the barrier layer and the buffer layer, and improving the service life of the OLED display device.

Abstract: Apparatus and methods to deposit a film using a batch processing chamber with a plurality of heating zones are described. The film is deposited on one or more substrates and the uniformity of the deposition thickness is determined at a plurality of points. The heating zones set points are applied to a sensitivity matrix and new temperature or power set points for the heating zones are determined and set. One or more substrates are processed using the new set points and the thickness uniformity is determined and may be adjusted again to increase the uniformity.

Abstract: The present invention provides a method for forming a semiconductor structure, the method includes: firstly, a substrate having a recess disposed therein is provided, wherein the substrate comprises a silicon substrate, next, a first element is formed in the recess and arranged along a first direction, wherein the first element is made of an oxidation semiconductor material, afterwards, a dielectric layer is formed on the first element, and a second element is formed on dielectric layer and arranged along the first direction, wherein the second element is used as the gate structure of a transistor structure.

Abstract: A vertically oriented treatment chamber for the processing of a flux-free solder ball (or plated solder ball) loaded wafer chip. A treatment chamber comprises a first or upper heater at an upper end of the treatment chamber and a second or lower heater at a lower end of the treatment chamber. The treatment chamber includes a centrally disposed, preloaded flux free solder ball loaded wafer chip support ring movable upwardly and downwardly within the treatment chamber in response to temperature sensed monitoring of a wafer chip supported on the wafer chip support ring.