Abstract: A manufacturing method of a metal gate structure includes the following steps. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. The silicon-containing work function layer includes a vertical portion and a horizontal portion. Finally, the gate trench is filled up with a conductive metal layer.

Abstract: An imaging device with excellent imaging performance is provided. In the imaging device, a first layer, a second layer, and a third layer have a region overlapping with one another, the first layer and the second layer each include transistors, and the third layer includes a photoelectric conversion element. Off-state currents of the transistors formed in the first layer are lower than those of the transistors formed in the second layer, and field-effect mobilities of the transistors formed in the second layer are higher than those of the transistors formed in the first layer.

Abstract: A lighting apparatus includes an LED light source radiationally coupled to a composite material including a phosphor of formula I and a thermally conductive material dispersed in at least a portion of a binder material. The thermally conductive material includes a material selected from the group consisting of indium oxide, tin oxide, indium tin oxide, calcium oxide, barium oxide, strontium oxide, aluminum hydroxide, magnesium hydroxide, calcium hydroxide, barium hydroxide, strontium hydroxide, zinc hydroxide, aluminum phosphate, magnesium phosphate, calcium phosphate, barium phosphate, strontium phosphate, diamond, graphene, polyethylene nanofibers, carbon nanotubes, silver metal nanoparticles, copper metal nanoparticles, gold metal nanoparticles, aluminum metal nanoparticles, boron nitride, silicon nitride, an alkali metal halide, calcium fluoride, magnesium fluoride, a compound of formula II, and combinations thereof.

Abstract: To miniaturize metal columns. A semiconductor device includes a metal column (14) that extends in a stretching direction; a polymer layer (16) that surrounds the metal column from a direction crossing the stretching direction; and a guide (12) that surrounds the polymer layer in the crossing direction so as to be spaced from the metal column with the polymer layer interposed therebetween. A method for manufacturing semiconductor devices includes a step of filling a mixture (20) containing metal particles (22) and polymers (24) in a guide (12); and a step of subjecting the mixture to a heat treatment so that the polymers agglomerate to the guide to form a polymer layer (16) that makes contact with the guide and the metal particles agglomerate away from the guide with the polymer layer interposed therebetween to form a metal column (14) that stretches in a stretching direction of the guide from the metal particles.

Abstract: A method for making a semiconductor device may include forming a plurality of stacked groups of layers on a semiconductor substrate, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include implanting a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region, and performing an anneal of the plurality of stacked groups of layers and semiconductor substrate and with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region.

Abstract: A semiconductor device having metal gate includes a substrate, a metal gate formed on the substrate, a pair of spacers formed on sidewalls of the metal gate, a contact etch stop layer (CESL) covering the spacers, an insulating cap layer formed on the metal gate, the spacers and the CESL, and an ILD layer surrounding the metal gate, the spacers, the CESL and the insulating cap layer. The metal gate, the spacers and the CESL include a first width, and the insulating cap layer includes a second width. The second width is larger than the first width. And a bottom of the insulating cap layer concurrently contacts the metal gate, the spacers, the CESL, and the ILD layer.

Abstract: Formation methods of a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate and forming a source/drain structure adjacent to the gate stack. The method also includes forming a cap element over the source/drain structure. The cap element has a top surface and a side surface, and a width ratio of the top surface to the side surface of the cap element is in a range from about 0.125 to about 1.

Abstract: A transient voltage suppressor (TVS) is constructed as an NPN bipolar transistor including individually optimized collector-base and emitter-base junctions both with avalanche mode breakdown. The TVS device is constructed using a base that includes a lightly doped base region bordered by a pair of more heavily doped base regions. The two more heavily doped base regions are used to form the collector-base junction and the emitter-base junction both as avalanche breakdown junctions. The lightly doped base region between the collector-base and emitter-base doping regions ensures low leakage current in the TVS device. In this manner, the TVS bipolar transistor of the present invention provides high surge protection with robust clamping while ensuring low leakage current.

Abstract: Some embodiments include a semiconductor construction which has one or more openings extending into a substrate. The openings are at least partially filled with dielectric material comprising silicon, oxygen and carbon. The carbon is present to a concentration within a range of from about 3 atomic percent to about 20 atomic percent. Some embodiments include a method of providing dielectric fill across a semiconductor construction having an opening extending therein. The semiconductor construction has an upper surface proximate the opening. The method includes forming photopatternable dielectric material within the opening and across the upper surface, and exposing the photopatternable dielectric material to patterned actinic radiation.

Abstract: A method of making a semiconductor device comprises forming a first channel region comprising a first channel region material and a second channel region comprising a second channel region material; disposing a gate dielectric on the first channel region and second channel region; depositing a work function modifying material on the gate dielectric; disposing a mask over the work function modifying material deposited on the gate dielectric disposed on the first channel region; removing the work function modifying material from the unmasked gate dielectric disposed on the second channel region; removing the mask from the work function modifying material deposited on the gate dielectric disposed on the first channel region; forming a first gate electrode on the work function modifying material deposited on the first channel region and forming a second gate electrode on the gate dielectric disposed on the second channel region.

Abstract: Disclosed herein are a metal-graphene heterojunction metal interconnect, a method of forming the same, and a semiconductor device including the same. The method includes: a) forming a carbon source layer by depositing a carbon source on a top surface of a substrate; b) forming a metal catalyst layer by depositing a metal catalyst on the carbon source layer; and c) carrying out heat treatment on the substrate comprising the carbon source layer and the metal catalyst layer. The graphene can be formed by carrying out the heat treatment only once irrespectively of the number of substrates, and accordingly to the manufacturing time and manufacturing cost of the metal interconnect are reduced, and a damage to the metal interconnect by the heat treatment is not caused.

Abstract: Provided is a display apparatus capable of reducing generation of defects such as a disconnection during manufacturing processes, while ensuring longer lifespan thereof. The display apparatus includes: a substrate including a bending area between a first area and a second area to be bent in the bending area about a bending axis, the substrate including a first substrate and a second substrate that are stacked; a first intermediate line at least partially located in the bending area, and located between the first substrate and the second substrate; and a first upper line over the second substrate to be electrically connected to the first intermediate line via a first contact hole in the second substrate.

Abstract: The present invention relates to new semiconducting compounds having at least one optionally substituted azino[1,2,3]thiadiazole moiety. The compounds disclosed herein can exhibit high carrier mobility and/or efficient light absorption/emission characteristics, and can possess certain processing advantages such as solution-processability and/or good stability at ambient conditions.

Abstract: Many of the physical properties of a silicon semiconductor have already been understood, whereas many of the physical properties of an oxide semiconductor have been still unclear. In particular, an adverse effect of an impurity on an oxide semiconductor has been still unclear. In view of the above, a structure is disclosed in which an impurity that influences electrical characteristics of a semiconductor device including an oxide semiconductor layer is prevented or is eliminated. A semiconductor device which includes a gate electrode, an oxide semiconductor layer, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer and in which the nitrogen concentration in the oxide semiconductor layer is 1×1020 atoms/cm3 or less is provided.

Abstract: A semiconductor structure includes a substrate and a first element disposed in the substrate and arranged along a first direction. The first element is made of a semiconductor oxide material. The semiconductor structure also includes a dielectric layer disposed on the first element, and a second element, disposed on the dielectric layer and arranged along the first direction. The second element is used as a gate of a transistor structure.

Abstract: Embodiments of the present disclosure disclose a thin film transistor, a fabrication method thereof, a repair method thereof, and an array substrate. The thin film transistor comprises a gate electrode (12), a gate insulating layer (13), an active layer (14), a source electrode (16) and a drain electrode (17). The source electrode (16) comprises a first source electrode portion (161) and a second source electrode portion (162) independent from each other, the first source electrode portion (161) and the second source electrode portion (162) are electrically connected with the active layer (14), respectively; and/or, the drain electrode (17) comprises a first drain electrode portion (171) and a second drain electrode portion (172) independent from each other, the first drain electrode portion (171) and the second drain electrode portion (172) are electrically connected with the active layer (14), respectively.

Abstract: A method of forming a semiconductor device includes following steps. First of all, plural mandrel patterns are formed on a target layer. Then, plural capping layers are formed to cover a top region and sidewalls of each of the mandrel patterns, respectively. Next, plural spacers are formed at two sides of each of the capping layers, respectively. Following these, a portion of the spacers and the capping layers covered on the top regions of the mandrel patterns are simultaneously removed, and the capping layers is then removed completely.

Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a first surface including a plurality of conductive pads and a second surface; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate. The insulating protective layer includes at least an opening for exposing at least one of the conductive pads, and the at least the passive component is directly provided on the conductive pad exposed from the opening.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a stackable semiconductor device with small size and fine pitch and a method of manufacturing thereof.

Abstract: A display apparatus includes a substrate including a display area displaying an image and a peripheral area outside the display area, a main wiring and an auxiliary wiring disposed in an identical layer in the peripheral area, the main wiring being disposed closer to the display area than the auxiliary wiring, a dam configured to cover at least a part of the main wiring, the auxiliary wiring being spaced apart from the dam, and a connecting wiring configured to connect the main wiring to the auxiliary wiring, and a thin-film encapsulation layer configured to seal the display area and the peripheral area.