Patents Examined by Colleen Matthews
  • Patent number: 9780522
    Abstract: The system and method for modifying the output beam parameters of a plurality of laser diode array sources comprises scalable pump sources for use with diode pumped alkali lasers. The present invention optimizes a diode laser pump source by spectrally-narrowing stacks of diode laser array bars using a single external cavity outfitted with a proprietary step-mirror and cylindrical optical elements. The system and method of the present invention multiplies by one-hundred fold the number of stacks that can be narrowed, vastly increasing the attainable power output by utilizing beam-splitters.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: October 3, 2017
    Assignee: University of New Hampshire
    Inventors: F. William Hersman, Jan Distelbrink
  • Patent number: 9356161
    Abstract: A semiconductor device includes: a photoelectric conversion section made of semiconductor; a color filter made of an inorganic material to which a metal ion is added; and a getter film formed between the photoelectric conversion section and the color filter and configured to trap the metal ion.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: May 31, 2016
    Assignee: Sony Corporation
    Inventor: Tomoko Miki
  • Patent number: 9343522
    Abstract: A ceramic powder for use in a grain boundary insulated semiconductor ceramic that has an excellent ESD withstanding voltage, a semiconductor ceramic capacitor using the ceramic powder, and a manufacturing method therefor. The ceramic powder for use in a SrTiO3 based grain boundary insulated semiconductor ceramic has a specific surface area of 4.0 m2/g or more and 8.0 m2/g or less, and a cumulative 90% grain size D90 of 1.2 ?m or less.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: May 17, 2016
    Inventors: Mitsutoshi Kawamoto, Atsushi Sano, Tatsuya Ishikawa, Yasutomo Kobayashi, Yoshihiro Fujita, Yuki Kimura, Yuichi Kusano
  • Patent number: 9324586
    Abstract: A chip-packaging module for a chip is provided, the chip-packaging module including a chip including a first chip side, wherein the first chip side includes an input portion configured to receive a signal; a chip carrier configured to be in electrical connection with the first chip side, wherein the chip is mounted to the chip carrier via the first chip side; and a mold material configured to cover the chip on at least the first chip side, wherein at least part of the input portion is released from the mold material.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: April 26, 2016
    Inventor: Horst Theuss
  • Patent number: 9318333
    Abstract: In patterning a transistor, some of a layer of gate dielectric material is allowed to remain over a semiconductor substrate upon which the transistor is formed. This remaining dielectric material retards the implantation of dopants into the underlying substrate, effectively lengthening a channel region of the transistor. This mitigates unwanted short channel effects, such as leakage currents, for example, and thus mitigates yield loss by establishing a transistor that performs in a more predictable or otherwise desirable manner.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: April 19, 2016
    Inventors: Vidyut Gopal, Shankar Sinha, Jean Yee-Mei Yang, Phillip L. Jones
  • Patent number: 9306134
    Abstract: An encapsulating composition for a light emitting device includes a transparent resin, a plurality of light scattering particles distributed throughout the transparent resin and having an average particle size ranging from 190 nm to 450 nm, and a plurality of phosphor particles distributed throughout the transparent resin. A light emitting device includes the encapsulating composition and a light emitting diode that is encapsulated by the encapsulating composition.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: April 5, 2016
    Inventors: Yuan-Li Liao, Chang-Hung Lee
  • Patent number: 9293257
    Abstract: A solid-state electronic device according to the present invention includes: an oxide layer (possibly containing inevitable impurities) that is formed by heating, in an atmosphere containing oxygen, a precursor layer obtained from a precursor solution as a start material including both a precursor containing bismuth (Bi) and a precursor containing niobium (Nb) as solutes, the oxide layer consisting of the bismuth (Bi) and the niobium (Nb); wherein the oxide layer is formed by heating at a heating temperature from 520° C. to 650° C.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: March 22, 2016
    Assignee: Japan Science and Technology Agency
    Inventors: Tatsuya Shimoda, Eisuke Tokumitsu, Masatoshi Onoue, Takaaki Miyasako
  • Patent number: 9287502
    Abstract: Resistance variable memory cell structures and methods are described herein. One or more resistance variable memory cell structures include a first electrode common to a first and a second resistance variable memory cell, a first vertically oriented resistance variable material having an arcuate top surface in contact with a second electrode and a non-arcuate bottom surface in contact with the first electrode; and a second vertically oriented resistance variable material having an arcuate top surface in contact with a third electrode and a non-arcuate bottom surface in contact with the first electrode.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: March 15, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Eugene P Marsh, Timothy A. Quick
  • Patent number: 9281187
    Abstract: The invention provides a method for manufacturing a nitride semiconductor device that grows a multilayer film of a III-V group nitride semiconductor in a reaction furnace into which a III group element raw material gas and a V group element raw material gas are introduced, the method including: growing a first nitride semiconductor layer at a first raw material gas flow rate of the V group element raw material gas and a first carrier gas flow rate; and growing a second nitride semiconductor layer at a second raw material gas flow rate of the V group element raw material gas lower than the first raw material gas flow rate and a second carrier gas flow rate higher than the first carrier gas flow rate, wherein the first nitride semiconductor layer and the second nitride semiconductor layer are stacked.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: March 8, 2016
    Inventors: Ken Sato, Hirokazu Goto, Hiroshi Shikauchi, Keitaro Tsuchiya, Masaru Shinomiya, Kazunori Hagimoto
  • Patent number: 9269598
    Abstract: A semiconductor device has a first conductive layer formed over a sacrificial substrate. A first integrated passive device (IPD) is formed in a first region over the first conductive layer. A conductive pillar is formed over the first conductive layer. A high-resistivity encapsulant greater than 1.0 kohm-cm is formed over the first IPD to a top surface of the conductive pillar. A second IPD is formed over the encapsulant. The first encapsulant has a thickness of at least 50 micrometers to vertically separate the first and second IPDs. An insulating layer is formed over the second IPD. The sacrificial substrate is removed and a second semiconductor die is disposed on the first conductive layer. A first semiconductor die is formed in a second region over the substrate. A second encapsulant is formed over the second semiconductor die and a thermally conductive layer is formed over the second encapsulant.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: February 23, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Jianmin Fang, Kang Chen, Haijing Cao
  • Patent number: 9263396
    Abstract: A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, the first and second regions being isolated from each other, a plurality of transistors formed in the first region, an alignment mark formed in the second region, the alignment mark having a plurality of active regions in a first direction, and a dummy gate structure formed over the alignment mark, the dummy gate structure having a plurality of lines in a second direction different from the first direction.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Liang Shen, Ming-Yuan Wu, Chiung-Han Yeh, Kong-Beng Thei, Harry-Hak-Lay Chuang
  • Patent number: 9263575
    Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: February 16, 2016
    Assignee: SK Hynix Inc.
    Inventors: Jin-Ku Lee, Young-Ho Lee, Mi-Ri Lee
  • Patent number: 9263652
    Abstract: A semiconductor light-emitting device includes a semiconductor region having a light-emitting structure, an electrode layer formed on the semiconductor region, and a reflective protection structure extending exposing the upper surface of the electrode layer and covering the semiconductor region adjacent to the electrode layer.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: February 16, 2016
    Inventors: Ju-heon Yoon, Gi-bum Kim, Sang-yeon Kim, Sang-yeob Song, Won-goo Hur
  • Patent number: 9236534
    Abstract: A light emitting diode package, a light source module and a backlight unit including the same are provided. A plurality of light emitting diode packages are arranged on a printed circuit board without interference therebetween, by forming lines therein.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: January 12, 2016
    Assignee: LG Display Co., Ltd.
    Inventors: SeungJoon Lee, DongHun Lee
  • Patent number: 9236276
    Abstract: In a manufacturing method of a semiconductor device, a semiconductor chip is sealed with a resin, and then a laser is applied to remove the resin so that a part of the semiconductor chip is exposed. The semiconductor chip is made of a material that has a lower absorptivity of the laser than the resin and is not melted by the laser. The laser has a wavelength that passes through the semiconductor chip and has a lower absorptivity in the semiconductor chip than in the resin. The laser is applied to the resin from a side adjacent to one of plate surfaces of the semiconductor chip, so that the resin sealing the one of the plate surfaces is sublimated and removed and at least a part of the resin sealing the other of the plate surfaces is subsequently sublimated and removed by the laser having passed through the semiconductor chip.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: January 12, 2016
    Inventors: Koji Hashimoto, Masamoto Kawaguchi, Masahiro Honda, Takashige Saito
  • Patent number: 9236339
    Abstract: Disclosed herein is a plug via stacked structure including: a through hole plating layer plated on a through hole inner wall and around top and bottom of a through hole at thickness t; a via plug filled in an inner space of the through hole plating layer; a circuit pattern formed over the top and bottom of the through hole plating layer and the via plug and making a thickness t? formed on the through hole plating layer thicker than a thickness t; and a stacked conductive via filled in a via hole formed on the top of the through hole and formed at thickness ? from a top of the circuit pattern, wherein T?t?+? is satisfied, T represents a sum of the thicknesses t and t? and t? is a thickness of a portion of the circuit pattern formed on the via plug.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: January 12, 2016
    Inventors: Seung Wook Park, Christian Romero, Chang Bae Lee, Mi Jin Park
  • Patent number: 9236712
    Abstract: A frequency tuneable or chirped laser device is described that includes a laser cavity formed from a plurality of optical components. The optical components include a laser source for generating a beam of light, a spectral tuning element and one or more further optical components for directing the beam of light on to the spectral tuning element. At least one of the plurality of optical components is moveable in a first degree of freedom; such movement simultaneously altering the effective optical path length of the laser cavity and the tuning frequency of the spectral tuning element. The effective optical path length and the tuning frequency of the device are substantially insensitive to any movement of said at least one moveable optical component in degrees of freedom other than the first degree of freedom. This provides frequency tuning in which mode hopping is suppressed.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: January 12, 2016
    Assignee: RENISHAW PLC
    Inventors: David R McMurtry, Alan J Holloway
  • Patent number: 9230803
    Abstract: Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer. A conductive path may be present in the conductive interface, and the conductive path may be interrupted by one or more local electrical isolations. The local electrical isolation(s) may be positioned with the device such that at least one of the local electrical isolation(s) is located between a high voltage terminal and a low voltage terminal of the device.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: January 5, 2016
    Assignee: Epigan NV
    Inventors: Joff Derluyn, Stefan Degroote, Marianne Germain
  • Patent number: 9227838
    Abstract: A method (30) of forming a semiconductor package (20) entails applying (56) an adhesive (64) to a portion (66) of a bonding perimeter (50) of a base (22), with a section (68) of the perimeter (50) being without the adhesive (64). A lid (24) is placed on the base (22) so that a bonding perimeter (62) of the lid (24) abuts the bonding perimeter (50) of the base (22). The lid (24) includes a cavity (25) in which dies (38) mounted to the base (22) are located. A gap (70) is formed without the adhesive (64) at the section (68) between the base (22) and the lid (24). The structure vents from the gap (70) as air inside the cavity (25) expands during heat curing (72). Following heat curing (72), another adhesive (80) is dispensed in the section (68) to close the gap (70) and seal the cavity (25).
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: January 5, 2016
    Inventors: Stephen R. Hooper, Philip H. Bowles
  • Patent number: 9230858
    Abstract: A semiconductor device is manufactured by etching a semiconductor substrate including an active region, forming a bit line contact hole from which the active region is protruded, forming a first spacer exposing a top of the active region at each of an inner wall and a bottom of the bit line contact hole, forming a bit line contact plug and a bit line over the exposed active region, and forming a second spacer over the semiconductor substrate including not only the bit line contact plug but also the bit line.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: January 5, 2016
    Assignee: SK HYNIX INC.
    Inventors: Jae Young Kim, Mi Hyune You