Patents Examined by Cory Eskridge
  • Patent number: 10217863
    Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with two concentric gate structures, including forming one or more tubular vertical fins on a substrate, forming a first gate structure around an outer wall of at least one of the one or more tubular vertical fins, and forming a second gate structure within an inner wall of at least one of the one or more tubular vertical fins having the first gate structure around the outer wall.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Shogo Mochizuki, Junli Wang
  • Patent number: 10156505
    Abstract: The present invention discloses an analysis method of a tensioning process of a fine mask plate. The analysis method, based on the simulation function of ANSYS software, finds an appropriate tensile force for stretching a fine mask plate and a corresponding actual counterforce applied to a metal frame before each fine mask plate is welded onto the metal frame through establishing a finite element model of the fine mask plate and a finite element model of the metal frame. The analysis process requires no physical tests, thereby effectively avoiding damaging the fine mask plate and further effectively saving the test cost.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: December 18, 2018
    Assignees: BOE Technology Group Co., Ltd., Ordos Yuansheng Optoelectronics Co., Ltd.
    Inventors: Fengli Ji, Minghua Xuan, Shanshan Bai, Jiantao Liu, Jingbo Xu
  • Patent number: 10147786
    Abstract: A semiconductor body having first and second vertically spaced apart surfaces is formed. A gate trench that vertically extends from the first surface of the semiconductor body towards the second surface is formed. A gate electrode and a gate dielectric are formed in the gate trench. The gate dielectric electrically insulates the gate electrode from adjacent semiconductor material. A doped superjunction region vertically extending from a bottom of the gate trench towards the second surface of the semiconductor body is formed. The doped superjunction region includes first, second, and third doped pillars vertically extending from the first surface of the first semiconductor layer and directly adjoining one another. The second pillar is laterally centered between the first and third pillars and has an opposite conductivity type as the first and third pillars.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: December 4, 2018
    Assignee: Infineon Technologies AG
    Inventors: Alice Pei-Shan Hsieh, Hans-Joachim Schulze
  • Patent number: 10141230
    Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a substrate having a {100} crystallographic surface orientation, forming a second semiconductor layer on the substrate, patterning the first semiconductor layer and the second semiconductor layer into a first plurality of fins and a second plurality of fins, respectively, wherein the first and second plurality of fins extend vertically with respect to the substrate, covering the first plurality of fins and a portion of the substrate corresponding to the first plurality of fins, and epitaxially growing semiconductor layers on exposed portions of the second plurality of fins and on exposed portions of the substrate, wherein the epitaxially grown semiconductor layers on the exposed portions of the second plurality of fins increase a critical dimension of each of the second plurality of fins.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corproation
    Inventors: Marc A. Bergendahl, Kangguo Cheng, John R. Sporre, Sean Teehan
  • Patent number: 10134750
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: November 20, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuya Kato, Wataru Sakamoto, Fumitaka Arai
  • Patent number: 10128263
    Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: November 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok Cheon Baek, Young Woo Kim, Dong Sik Lee, Min Yong Lee, Woong Seop Lee
  • Patent number: 10126728
    Abstract: A method and a system collect via a MES, time-stamps of working-statuses of machines and operators, called also actors, for a calculation of a time-dependant component of OLE and OEE indicators in a manufacturing task. The method includes providing a token for assigning to an actor the responsibility of data provision, and defining two meta-statuses for a machine in a task, called operating and booked meta-status respectively. Each meta-status groups a set of machine statuses. A machine is defined to be in an operating meta-status when the machine is in a status engaged in the task and it is able to know and notify its own status. A machine is defined to be in a booked meta-status when the machine is in a status engaged in the task and it is unable to notify its own status.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: November 13, 2018
    Assignee: Siemens Aktiengesellschaft
    Inventors: Andrea Gozzi, Katia Lupi
  • Patent number: 10128383
    Abstract: A thin film transistor array substrate includes a first conductive pattern group including a gate line extending along a first direction, data lines extending along a second direction crossing the first direction and spaced apart from each other along the second direction with the gate line there between, and a gate electrode protruding from the gate line, an active pattern disposed on the gate electrode to overlap the gate electrode, a second conductive pattern group including a bridge pattern coupling the data lines, a source electrode extending to an upper portion of the active pattern from the bridge pattern and a drain electrode spaced apart from the source electrode, facing the source electrode and disposed on the active pattern and metal patterns each stacked between the active pattern and the source electrode and between the active pattern and the drain electrode.
    Type: Grant
    Filed: January 3, 2016
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Jong Hyun Choung
  • Patent number: 10114052
    Abstract: Disclosed herein are systems and methods for estimating a period and frequency of a waveform. In one embodiment a system may comprise an input configured to receive a signal comprising a representation of the waveform. A period determination subsystem may calculate an estimated period of the signal based on a period determination function. An estimated period adjustment subsystem may determine an adjustment to the estimated period based on a result of the period determination function. A quality indicator subsystem configured to evaluate a measurement quality indictor function based on the estimated period, and to selectively update the period of the waveform based on the measurement quality indicator. A control action subsystem configured to implement a control action based on the period of the waveform.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: October 30, 2018
    Assignee: Schweitzer Engineering Laboratories, Inc.
    Inventors: Bogdan Z. Kasztenny, Tony J. Lee
  • Patent number: 10101162
    Abstract: One embodiment provides a method for improving cartographic data using utility data, the method including: obtaining cartographic information; obtaining geo-location information associated with at least one utility asset; utilizing at least one processor to execute computer code that performs the steps of: generating, based on the geo-location information, a cartographic representation of the at least one utility asset; and modifying, based on the cartographic representation, the cartographic information. Other aspects are described and claimed.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: October 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Vijay Arya, Sambaran Bandyopadhyay, Ramachandra Kota, Rajendu Mitra
  • Patent number: 10103161
    Abstract: Die cracking of a three dimensional memory device may be reduced by adding offsets to backside contact via structures. Each backside contact via structure can include laterally extending portions that extend along a first horizontal direction adjoined by adjoining portions that extend along a horizontal direction other than the first horizontal direction. In order to preserve periodicity of memory stack structures extending through an alternating stack of insulating layers and electrically conductive layers, the distance between an outermost row of a string of memory stack structures between a pair of backside contact via structures and a most proximal backside contact via structure can vary from a laterally extending portion to another laterally extending portion within the most proximal backside contact via structure. Source shunt lines that are parallel to bit lines can be formed over a selected subset of offset portions of the backside contact via structures.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: October 16, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fumitoshi Ito, Masaaki Higashitani, Cheng-Chung Chu, Jayavel Pachamuthu, Tuan Pham
  • Patent number: 10094815
    Abstract: A method and system are described that may be used for exploration, production and development of hydrocarbons. The method and system may include analyzing a sample for a geochemical signature, wherein the geochemical signature includes a multiply substituted isotopolog signature and/or a position specific isotope signature. Then, the historical temperature, type of alteration and/or extent of alteration may be determined from the signature(s) and used to develop or refine an exploration, development or production strategy.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: October 9, 2018
    Assignee: ExxonMobil Upstream Research Company
    Inventors: Michael Lawson, Brian K. Peterson, Cara L. Davis, David R. Converse, John M. Eiler
  • Patent number: 10090149
    Abstract: A method of manufacturing a semiconductor device includes: forming a base film containing a first element and carbon on a substrate by supplying a film forming gas to the substrate; and oxidizing the base film by supplying an oxidizing gas to the substrate to modify the base film into a C-free oxide film containing the first element.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: October 2, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yoshitomo Hashimoto, Yoshiro Hirose
  • Patent number: 10090170
    Abstract: A method is provided for fabricating a semiconductor structure. The method includes forming a base substrate including a substrate and a stress layer formed in the substrate, where a top surface of the stress layer is higher than a surface of the substrate. The method also includes forming a first cover layer, where a first growth rate difference exists between growth rates of the first cover layer on the top surface of the stress layer and the first cover layer on a side surface of the stress layer. Further, the method includes forming a second cover layer, where a second growth rate difference exists between growth rates of the second cover layer on the top surface of the stress layer and the second cover layer on the side surface of the stress layer, and the second growth rate difference is larger than the first growth rate difference.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: October 2, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Lan Jin
  • Patent number: 10088600
    Abstract: The invention relates to a weather recognition method and device based on image information detection, including: obtaining an image extracting multiple first image features of the image with respect to each preset type of weather using a number of first preset algorithms preset correspondingly for different preset types of weather; inputting the multiple first image features to a preset multi-kernel classifier, the multi-kernel classifier performing classification according to the image features to identify the weather in which the image was taken. The multi-kernel classifier is realized by: selecting a first preset number of image samples for each of the preset types of weather; for the image samples of this type of weather, extracting the first image features of each image sample according to the first preset algorithm corresponding to this preset type of weather; and performing machine learning for the first image features according to a preset multi-kernel learning algorithm.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: October 2, 2018
    Assignee: BEIJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS
    Inventors: Huadong Ma, Huiyuan Fu, Zheng Zhang
  • Patent number: 10090228
    Abstract: A semiconductor package or device includes a leadframe defining a plurality of leads which are arranged and partially etched in a manner facilitating a substantial reduction in burr formation resulting from a saw singulation process used to complete the fabrication of the semiconductor device. In one embodiment, the semiconductor device includes a die pad defining multiple peripheral edge segments. In addition, the semiconductor device includes a plurality of leads that are provided in a prescribed arrangement. At least one semiconductor die is connected to the top surface of the die pad and further electrically connected to at least some of the leads. At least portions of the die pad, the leads, the lands, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die pad and the leads being exposed in a common exterior surface of the package body.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: October 2, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Hong Bae Kim, Hyun Jun Kim, Hyung Kook Chung
  • Patent number: 10086960
    Abstract: A diagnostic method for a container processing machine including a rotating conveyor, and processing units carried by the rotating conveyor and designed to engage at least one container to carry out processing operations is disclosed. The method includes operatively coupling a first set of monitoring sensors to the processing units on-board the processing machine to monitor relevant operating parameters. The method also includes controlling the processing units to execute test operations in lieu of processing operations. The method further includes acquiring measurement data from the first set of monitoring sensors during the test operations. The method further includes processing the acquired measurement data to provide maintenance information on the reliability of at least one of the processing units or the processing machine.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: October 2, 2018
    Assignee: Sidel S.p.A. Con Socio Unico
    Inventors: Federica Sorbi, Michele Ollari, Alessandro Gorbi
  • Patent number: 10084017
    Abstract: A switch device includes: a first electrode; a second electrode disposed to oppose the first electrode; a switch layer provided between the first electrode and the second electrode, and including at least one or more kinds of chalcogen elements and one or more kinds of first elements out of the one or more kinds of chalcogen elements, the one or more kinds of first elements, and a second element including one or both of oxygen (O) and nitrogen (N), the one or more kinds of chalcogen elements being selected from tellurium (Te), selenium (Se), and sulfur (S), and the one or more kinds of first elements being selected from boron (B), carbon (C), and silicon (Si).
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: September 25, 2018
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Kazuhiro Ohba, Hiroaki Sei
  • Patent number: 10079339
    Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: September 18, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Kerry Joseph Nagel, Chaitanya Mudivarthi, Sanjeev Aggarwal
  • Patent number: 10074621
    Abstract: Provided is an electronic package, including: a carrier, an electronic component disposed on the carrier, and an antenna structure, wherein the antenna structure has a plurality of spacing members and at least one wire connected among the spacing members. No additional layout area is required to be formed on a surface of the carrier, such that the objective of miniaturization can be achieved.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: September 11, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chih-Hsien Chiu, Chi-Pin Tsai, Chi-Liang Shih, Ming-Fan Tsai, Chia-Yang Chen