Patents Examined by Cory Eskridge
  • Patent number: 9921116
    Abstract: A system including a current module, a second module, and a temperature module. The current module is configured to determine an amount of current drawn from a power source by a hydraulic pump of a transmission based on a current signal received from a current sensor. The current signal is indicative of the current drawn by the hydraulic pump. The second module is configured to determine (i) a speed of the hydraulic pump based on a speed signal received from a speed sensor, or (ii) an output torque of the hydraulic pump based on the amount of current drawn by the hydraulic pump. The speed signal is indicative of the speed of the hydraulic pump. The temperature module is configured to estimate a temperature of a hydraulic fluid circulated by the hydraulic pump based on (i) the amount of current drawn by the hydraulic pump, and (ii) the speed or the output torque of the hydraulic pump. The second module is configured to adjust the speed of the hydraulic pump based on the temperature of the hydraulic fluid.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: March 20, 2018
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Mehmet Emin Inan, Paul A. Adam
  • Patent number: 9917093
    Abstract: A three-dimensional memory device includes a plurality of planes, each having a respective alternating stack, strings of memory stack structures which extends through the respective alternating stack, and backside contact via structures vertically extending through the respective alternating stack, extending generally along the first horizontal direction, and laterally separating neighboring pairs of strings of memory stack structures along a second horizontal direction. A first plane includes a first plurality of strings that are laterally spaced apart along the second horizontal direction by a first plurality of backside contact via structures.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: March 13, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Cheng-Chung Chu, Jayavel Pachamuthu, Tuan Pham, Fumitoshi Ito, Masaaki Higashitani
  • Patent number: 9911594
    Abstract: Methods for forming fin structure with desired materials formed on different locations of the fin structure using a selective deposition process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes forming a patterned self-assembled monolayer on a circumference of a structure formed on a substrate, wherein the patterned self-assembled monolayer includes a treated layer formed among a self-assembled monolayer, and performing an atomic layer deposition process to form a material layer predominantly on the self-assembled monolayer from the patterned self-assembled monolayer.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: March 6, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Srinivas D. Nemani, Ellie Y. Yieh, Ludovic Godet, Yin Fan
  • Patent number: 9905502
    Abstract: A method is disclosed of fabricating a microelectronic package comprising a substrate overlying the front face of a microelectronic element. A plurality of metal bumps project from conductive elements of the substrate towards the microelectronic element, the metal bumps having first ends extending from the conductive elements, second ends remote from the conductive elements, and lateral surfaces extending between the first and second ends. The metal bumps can be wire bonds having first and second ends attached to a same conductive pad of the substrate. A conductive matrix material contacts at least portions of the lateral surfaces of respective ones of the metal bumps and joins the metal bumps with contacts of the microelectronic element.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: February 27, 2018
    Assignee: Tessera, Inc.
    Inventor: Wael Zohni
  • Patent number: 9905436
    Abstract: A method for manufacturing a wafer level fan-out package includes attaching a semiconductor chip on a partial area of an IO pattern formed on one surface of a wafer, forming a first passivation layer on surfaces of the semiconductor chip and the wafer, forming an RDL (redistribution layer) that is electrically conducted with the IO pattern and the semiconductor chip, in a partial area of a top surface of the first passivation layer, and forming a second passivation layer on the top surface of the first passivation layer and a partial surface of the RDL.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: February 27, 2018
    Assignee: STS SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD.
    Inventors: You Jin Oh, Eun Dong Kim, Jong Won Lee, Jai Kyoung Choi
  • Patent number: 9893001
    Abstract: A semiconductor device includes a quadrilateral package with a first pair of opposed sides and a second pair of opposed sides. Both sides of the first pair of opposed sides are provided with electrical contact leads. Only one side of the second pair of opposed sides is provided with electrical contact leads. The side of the second pair of opposed sides without electrical contact leads is a leadless side. That side is not a molded side of the package, but rather is defined by a cut surface.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: February 13, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alberto Arrigoni, Alberto Da Dalt
  • Patent number: 9880133
    Abstract: A system for determining a material property is disclosed. In some embodiments, a method for determining a material property comprises receiving a set of material responses corresponding to a set of ultrasonic excitations. The set of material responses are determined using measurements to determine a peak response for each of the set of ultrasonic excitations. In some embodiments, a device for making non-destructive in-situ measurements of the elastic yield strength of a sample (e.g., a steel plate or pipeline wall) is disclosed. The device determines the yield strength of a specimen based on transducing ultrasonic waves within the medium and correlating quantifiable characteristics of the resulting frequency response to the intrinsic elastic nonlinearity of the material. In various embodiments, the device includes one or more electrodes, an acoustic termination, a horn, a flange, a collar, power electronics, signal processors, a memory, a user interface, or any other appropriate device component.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: January 30, 2018
    Assignee: Atlas Sensors, LLC
    Inventor: Philip J. Stephanou
  • Patent number: 9865691
    Abstract: A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: January 9, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Sameer P. Pendharkar, Jarvis Benjamin Jacobs
  • Patent number: 9859189
    Abstract: A thermally conductive sheet of the present invention includes a thermosetting resin (A) and an inorganic filler material (B) that is dispersed in the thermosetting resin (A). In the thermally conductive sheet of the present invention, at a frequency of 1 kHz and at a temperature of 100° C. to 175° C., the maximum value of a dielectric loss factor of a cured product of the thermally conductive sheet is less than or equal to 0.030, and a change in relative dielectric constant of the cured product of the thermally conductive sheet is less than or equal to 0.10.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: January 2, 2018
    Assignee: SUMITOMO BAKELITE CO., LTD.
    Inventors: Shunsuke Mochizuki, Kazuya Kitagawa, Yoji Shirato, Keita Nagahashi, Mika Tsuda, Satoshi Maji, Motomi Kurokawa, Kazuya Hirasawa
  • Patent number: 9853141
    Abstract: Higher voltage resistance is accomplished by expanding a depletion layer more quickly within a circumferential region. A semiconductor device includes an element region, in which an insulated gate type switching element is provided, and the circumferential region. A first trench and a second trench spaced apart from the first trench are provided in the front surface in the circumferential region. Insulating films are provided in the first trench and the second trench. A fourth region of the second conductivity type is provided so as to extend from a bottom surface of the first trench to a bottom surface of the second trench. A fifth region of the first conductivity type continuous from the third region is provided under the fourth region.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: December 26, 2017
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Jun Saito, Hirokazu Fujiwara, Tomoharu Ikeda, Yukihiko Watanabe, Toshimasa Yamamoto
  • Patent number: 9851227
    Abstract: In order to mitigate a need for reprogramming tire pressure sensors after tire rotation, tire change, etc., all sensors on a vehicle are preprogrammed with a lookup table that correlates modulation frequency to axle and wheel end positions on the vehicle. Dual antenna initiator coils are mounted to a vehicle such that each wheel end has one directional antenna directed toward it. Each initiator coil is programmed to modulate its transmission frequency by a predetermined modulation frequency such that each antenna transmits using a different modulation frequency. Each sensor receives a modulated signal, identifies the modulation frequency, and performs a table lookup to determine its axle and wheel end location. The sensor transmits its identified wheel end and axle location to a controller unit along with tire pressure status information for its wheel.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: December 26, 2017
    Assignee: BENDIX COMMERCIAL VEHICLE SYSTEMS LLC
    Inventor: Shawn D. Lammers
  • Patent number: 9853232
    Abstract: Disclosed is an organic light emitting device that may include a substrate having first to third light emitting parts; a first electrode in each of the first to third light emitting parts; a hole transport layer on the first electrode; first and second light emitting layers on the hole transport layer in the first and second light emitting parts, respectively; a common third light emitting layer on the first and second light emitting layers; a hole connection layer including a bipolar material and an electron transport material, wherein the hole connection layer in the first and second light emitting parts is provided between the common third light emitting layer and the first and second light emitting layers, and the hole connection layer in the third light emitting part is provided between the common third light emitting layer and the hole transport layer; a second electrode on the common third light emitting layer.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: December 26, 2017
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Jeongkyun Shin, Youngju Kim
  • Patent number: 9847413
    Abstract: N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: December 19, 2017
    Assignee: MaxPower Semiconductor Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng
  • Patent number: 9846426
    Abstract: A field programmable gate array (FPGA) in a machine health monitoring (MHM) module includes interface circuitry, vibration data processing circuitry, and tachometer data processing circuitry. The interface circuitry de-multiplexes a synchronous serial data stream comprising multiple multiplexed data channels, each containing machine vibration data or tachometer data, into separate input data streams. The vibration data processing circuitry comprises parallel processing channels for the separate input data streams containing vibration data, each channel including a highpass filter, two stages of integration circuits, a digital tracking bandpass filter, and multiple parallel scalar calculation channels. The tachometer data processing circuitry processes the tachometer data to generate RPM and other values. A cross-point switch in the FPGA distributes tachometer signals between MHM modules in a distributed control system, thereby allowing multiple modules to share tachometer information.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: December 19, 2017
    Assignee: Computational Systems, Inc.
    Inventor: John W. Willis
  • Patent number: 9843018
    Abstract: A display device includes a substrate including a peripheral region folded back to face a rear surface of the substrate, and a counter region facing the peripheral region; and a filling member held between the peripheral region and the counter region. The substrate is folded such that the display device includes a first overlapping portion where a part of the peripheral region is bonded with the counter region with an adhesive material being provided therebetween; a second overlapping portion where a part of the peripheral region is in direct contact with the filling member; and a third overlapping portion where a part of the peripheral region is bonded with the filling member with an adhesive material being provided therebetween.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: December 12, 2017
    Assignee: Japan Display Inc.
    Inventors: Naohisa Ando, Toshihiro Sato
  • Patent number: 9831147
    Abstract: In an embodiment, an electronic component includes a first dielectric layer including an organic component having a decomposition temperature of at least 180° C., a semiconductor die embedded in the first dielectric layer, a second dielectric layer arranged on a first surface of the first dielectric layer, the second dielectric layer including a photo definable polymer composition and defining two or more discrete openings having conductive material, and a first substrate arranged on the second dielectric layer and on the conductive material. One or more contact pads are arranged on an outermost surface of the first substrate.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: November 28, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Standing
  • Patent number: 9831100
    Abstract: Provided are methods for fabricating transistors using a gate last approach. These methods involve etching of titanium nitride and titanium carbide structures while preserving high k-dielectric structures. The titanium carbide structures may also include aluminum. Etching may be performed in one or more etching solutions, each including hydrogen peroxide. Titanium nitride and titanium carbide structures can be etched simultaneously (non-selectively) in the same etching solution that also includes hydrochloric acid, in addition to hydrogen peroxide, and maintained at about 25° C. and 85° C. In some embodiments, titanium nitride structures and titanium carbide structures may be etched separately (selectively) in different operations and using different etching solutions. The titanium nitride structures may be etched in a diluted hydrogen peroxide solution maintained at about 25° C. and 85° C.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: November 28, 2017
    Assignees: Intermolecular, Inc., International Business Machines
    Inventors: John Foster, Sean Lin, Muthumanickam Sankarapandian, Ruilong Xie
  • Patent number: 9831113
    Abstract: A method of manufacturing a semiconductor device includes forming a silicon nitride film having an opening portion on a semiconductor substrate, forming a silicon oxide film on the silicon nitride film and on a side face of the opening portion, performing an etching treatment to the silicon oxide film so that a sidewall is formed on the side face of the opening portion, forming a trench on the semiconductor substrate with use of the sidewall and the silicon nitride film as a mask, and forming an insulating layer in the trench. The step of forming the silicon oxide film includes oxidizing the silicon nitride film with a plasma oxidation method or a radical oxidation method.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: November 28, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Fumihiko Inoue, Yukio Hayakawa
  • Patent number: 9831275
    Abstract: A method for manufacturing a highly reliable semiconductor device is provided. The method includes the steps of: forming an oxide semiconductor film at a first temperature; processing the oxide semiconductor film into an island shape; not performing a process at a temperature higher than the first temperature, but depositing a material to be source and drain electrodes by a sputtering method; processing the material to form the source and drain electrodes; forming a protective insulating film, and then forming a first barrier film; adding excess oxygen or oxygen radicals to the protective insulating film through the first barrier film; performing heat treatment at a second temperature lower than 400° C. to diffuse the excess oxygen or oxygen radicals into the oxide semiconductor film; and removing part of the first barrier film and part of the protective insulating film by wet etching, and then forming a second barrier film.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: November 28, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Kenichi Okazaki, Daisuke Kurosaki, Masami Jintyou, Shunpei Yamazaki
  • Patent number: 9824918
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate, sequentially forming an etch stop layer and an interlayer dielectric layer on the semiconductor substrate, forming a copper metal interconnect structure in the interlayer dielectric layer, forming a copper layer in the copper metal interconnect structure, forming a cobalt layer on the copper layer, and forming an aluminum nitride layer on the cobalt layer. The stack of cobalt layer and copper layer effectively suppresses electromigration caused by diffusion of the copper layer into the interlayer dielectric layer, improves the adhesion between the copper layer and the etch stop layer, and prevents delamination.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: November 21, 2017
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Ming Zhou