Abstract: A method of processing a single-crystal member includes setting the peak energy density of a pulsed laser beam to a value in a range from 1 TW/cm2 to 100 TW/cm2, and applying the pulsed laser beam to the single-crystal member while positioning a converged point of the pulsed laser beam at a predetermined position spaced from an upper side of the single-crystal member to grow a fine hole and a amorphous region shielding the fine hole from the upper side of the single-crystal member, thereby forming a shield tunnel in the single-crystal member.

Abstract: A semiconductor device includes first to third semiconductor regions, first to fourth electrodes and a first insulating film. The first insulating film is provided between the third electrode and the first semiconductor region, between the third electrode and the second semiconductor region, between the third electrode and the third semiconductor region, and between the fourth electrode and the first semiconductor region. The first insulating film has a first insulating region, a second insulating region and a third insulating region. A first width in the first insulating region is different from a second width in the second insulating region. The first insulating region and the second insulating region are arranged in the direction. A third width of the third insulating region is constant along the second direction.

Abstract: A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.

Abstract: A method of isolating bad pixels on a wafer comprising the steps of determining physical locations of the bad pixels on the wafer, creating a mask based on the physical locations of the bad pixels, imprinting the mask onto the wafer, and hybridizing the wafer onto a readout integrated circuit (ROIC).

Abstract: A lateral bipolar junction transistor is fabricated using a semiconductor-on-insulator substrate. The transistor includes a germanium gradient within a doped silicon base region, there being an increasing germanium content in the direction of the collector region of the transistor. The use of a substrate including parallel silicon fins to fabricate lateral bipolar junction transistors facilitates the inclusion of both CMOS FinFET devices and lateral bipolar junction transistors having graded silicon germanium base regions on the same chip.

Abstract: A micromechanical component for a capacitive sensor device includes first and second electrodes. The first electrode is at least partially formed from a first semiconductor layer and/or metal layer, and at least one inner side of the second electrode facing the first electrode is formed from a second semiconductor layer and/or metal layer. A cavity is between the first and second electrodes. Continuous recesses are structured into the inner side of the second electrode and sealed off with a closure layer. At least one reinforcing layer of the second electrode and at least one contact element which is electrically connected to the first electrode, to the layer of the second electrode which forms the inner side, to at least one printed conductor, and/or to a conductive substrate area, are formed from at least one epi-polysilicon layer. Also described is a micromechanical component manufacturing method for a capacitive sensor device.

Abstract: Methods for forming fin structure with desired materials formed on different locations of the fin structure using a selective deposition process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes forming a patterned self-assembled monolayer on a circumference of a structure formed on a substrate, wherein the patterned self-assembled monolayer includes a treated layer formed among a self-assembled monolayer, and performing an atomic layer deposition process to form a material layer predominantly on the self-assembled monolayer from the patterned self-assembled monolayer.

Abstract: An electrochemical process for applying a conductive film onto a substrate having a seed layer includes placing the substrate into contact with an electrochemical plating bath containing cobalt or nickel, with the plating bath having pH of 4.0 to 9.0. Electric current is conducted through the bath to the substrate. The cobalt or nickel ions in the bath deposit onto the seed layer. The plating bath may contain cobalt chloride and glycine. The electric current may range from 1-50 milli-ampere per square cm. After completion of the electrochemical process, the substrate may be removed from the plating bath, rinsed and dried, and then annealed at a temperature of 200 to 400 C to improve the material properties and reduce seam line defects. The plating and anneal process may be performed through multiple cycles.

Abstract: The present invention provides a method for manufacturing a thin-film transistor substrate, which has a simple process and achieves an excellent contact interface between an oxide semiconductor layer and source/drain terminals through successive film forming so as to prevent crowding effect resulting from excessive contact resistance. Further, by using a metallic material containing tantalum to make the source/drain terminals and applying an etchant solution containing hydrogen peroxide to carry out etching in an etching process of the source/drain terminals, damages of the oxide semiconductor layer caused by traditional etchant solution can be prevented and quality of the thin-film transistor substrate can be enhanced.

Abstract: The present invention relates a packaging structure including: a carrier board and a cementing layer on the surface of the carrier board; chips and passive devices having functional side thereof attached to the cementing layer; and a sealing material layer for packaging and curing, the sealing material being formed on the carrier board on the side attached to the chips and the passive devices. The present invention integrates chips and passive devices and then packages the chips and the passive devices together, and is therefore a packaged product having not single-chip functionality but integrated-system functionality. The present invention is highly integrated, reduces interfering factors such as system-internal electric resistance and inductance, and accommodates growing demand for lighter, thinner, shorter, and smaller semiconductor packaging.

Abstract: Provided is a solar cell including a photoelectric conversion section having a first principal surface and a second principal surface, and a collecting electrode formed on the first principal surface of photoelectric conversion section. The photoelectric conversion section includes a semiconductor-stacked portion including a semiconductor junction, a first electrode layer which is a transparent electrode layer formed on the first principal surface side of the semiconductor-stacked portion, and a second electrode layer formed on the second principal surface side of the semiconductor-stacked portion. The collecting electrode includes a first electroconductive layer and a second electroconductive layer. In the manufacturing method, an insulating layer is formed on the first electrode layer, and the electrode layer exposed to the surface of the insulating layer-non-formed region is removed to eliminate a short circuit between the first and second electrode layers.

Abstract: Structures and methods are provided for forming fin structures. A first fin structure is formed on a substrate. A shallow-trench-isolation structure is formed surrounding the first fin structure. At least part of the first fin structure is removed to form a cavity. A first material is formed on one or more side walls of the cavity. A second material is formed to fill the cavity, the second material being different from the first material. At least part of the STI structure is removed to form a second fin structure including the first material and the second material. At least part of the first material that surrounds the second material is removed to fabricate semiconductor devices.

Abstract: A bipolar junction transistor includes an emitter, a base contact, a collector and a shallow trench isolation. The base contact has two base fingers that form a corner to receive the emitter. The collector has two collector fingers extending along the base fingers of the base contact. The shallow trench isolation is disposed in between the emitter and the base contact and in between the base contact and the collector.

Abstract: An embodiment semiconductor device includes a substrate such as a silicon or silicon-containing film, a pixel array supported by the substrate, and a metal stress release feature arranged around a periphery of the pixel array. The metal stress release feature may be formed from metal strips or discrete metal elements. The metal stress release feature may be arranged in a stress release pattern that uses a single line or a plurality of lines. The metal stress release pattern may also use metal corner elements at ends of the lines.

Abstract: Discussed is an organic light emitting display device that may include a first pixel on a substrate; a switching transistor with a first active layer provided inside the first pixel; a driving transistor with a second active layer provided inside the first pixel; a first light shielding layer overlapping the second active layer; and a second light shielding layer overlapping the first active layer, wherein the first light shielding layer is connected with the driving transistor, and the second light shielding layer is electrically insulated from the first light shielding layer.

Abstract: The semiconductor device includes an oxide semiconductor film having a first region and a pair of second regions facing each other with the first region provided therebetween, a gate insulating film over the oxide semiconductor film, and a first electrode overlapping with the first region, over the gate insulating film. The first region is a non-single-crystal oxide semiconductor region including a c-axis-aligned crystal portion. The pair of second regions is an oxide semiconductor region containing dopant and including a plurality of crystal portions.

Abstract: A method is disclosed of fabricating a microelectronic package comprising a substrate overlying the front face of a microelectronic element. A plurality of metal bumps project from conductive elements of the substrate towards the microelectronic element, the metal bumps having first ends extending from the conductive elements, second ends remote from the conductive elements, and lateral surfaces extending between the first and second ends. The metal bumps can be wire bonds having first and second ends attached to a same conductive pad of the substrate. A conductive matrix material contacts at least portions of the lateral surfaces of respective ones of the metal bumps and joins the metal bumps with contacts of the microelectronic element.

Abstract: A substrate device for electronic circuits or devices includes a first substrate section including a first plurality of layers attached to each other having a first orientation (x2) and a second substrate section including a second plurality of layers attached to each other. The second plurality of layers have a second orientation (x3). The first orientation (x2) and the second orientation (x3) are angled (?) with respect to one another.

Abstract: N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).

Abstract: A method for fabricating a field-effect transistor includes forming a spacer adjacent to sidewalls of a gate structure. The method further includes forming silicide regions in a substrate adjacent to the spacer. The method further includes depositing a first interlayer dielectric layer over the substrate. The method further includes exposing a top surface of the gate structure. The method further includes depositing a contact etch stop layer over the first interlayer dielectric layer and the top surface of the gate structure. The method further includes patterning the contact etch stop layer to remove a portion of the contact etch stop layer over the silicide regions, wherein the contact etch stop layer over the gate structure is maintained.